CN102723307A - Preparation method of array substrate and TFT structure - Google Patents

Abstract

The invention discloses a method for preparing an array substrate. After preparing source-drain electrodes and lead wires on a gate insulating layer, a semiconductor layer is deposited; Expose the pattern of electrodes and leads; remove the semiconductor where the photoresist is completely exposed and then peel off the photoresist; deposit a passivation layer, perform a patterning process on the passivation layer and the semiconductor layer, form a drain electrode via hole, and cut off adjacent data The semiconductor layer connection between the lines and the semiconductor layer connection between the adjacent leads in the edge area; covering the indium tin oxide ITO layer, and performing a patterning process to form a pixel electrode pattern. The invention also discloses a TFT structure. Through the invention, the carrier can be directly conducted from the source electrode to the drain through the gate insulating layer and the amorphous silicon semiconductor layer during the flow process, thereby greatly improving the characteristics of the TFT, and the mask The number of plates used remains the same, which can speed up the processing speed, increase the production capacity and reduce the cost.

Description

Method for preparing array substrate and TFT structure

technical field

The invention relates to array (Array) substrate preparation technology, in particular to a method for preparing an array substrate and a thin film field effect transistor (Thin Film Transistor, TFT) structure.

Background technique

Flat panel display technology has developed rapidly in the past ten years, and great progress has been made in terms of screen size and display quality. After continuous efforts, the performance of liquid crystal displays (Liquid Crystal Display, LCD) has reached the level of traditional cathode ray tube (Cathode Ray Tube, CRT) displays, and there is a tendency to replace CRT displays.

With the continuous expansion of the production of flat panel display products, the competition among various manufacturers is becoming increasingly fierce. While continuously improving product performance, manufacturers are also making continuous efforts to reduce product production costs, thereby enhancing market competitiveness.

TFT is an important part of the LCD array substrate. In traditional amorphous silicon TFT devices, the amorphous silicon bottom method is mainly used for design. Figure 1 is a schematic cross-sectional view of a TFT device on an array substrate prepared by the amorphous silicon bottom method. , in Fig. 1, 1 is a glass substrate, 2 is a gate insulating layer, 3 is a gate electrode, 4 is a source-drain electrode, 5 is an amorphous silicon semiconductor layer, 6 is a photoresist layer, and 7 is a photoresist removal for backside exposure. Area, 8 is a passivation layer, 9 is a pixel electrode, based on the structure shown in Figure 1, the conduction layer of the carrier is at the interface between the gate insulating layer and the amorphous silicon semiconductor layer, so that electrons must pass through twice The thickness of the amorphous silicon semiconductor layer can be transmitted between the source and the drain, thus affecting the conductivity of the TFT. However, if the amorphous silicon top-mounted method is used, it is often necessary to design an additional mask, and the processing is slow, the production capacity is low, and the manufacturing cost is high.

Contents of the invention

In view of this, the main purpose of the present invention is to provide a method for preparing an array substrate and a TFT structure, which can improve the conductive properties of the TFT, and have faster processing speed, higher productivity, and lower manufacturing cost.

In order to achieve the above object, technical solution of the present invention is achieved in that way:

A method of preparing an array substrate, comprising:

After preparing gate electrodes and leads on the glass substrate, depositing a gate insulating layer;

After preparing source and drain electrodes and leads on the gate insulating layer, depositing a semiconductor layer;

Coating photoresist on the semiconductor layer, and then using gate electrodes and leads, and patterns of source and drain electrodes and leads on the back of the glass substrate to expose the photoresist to a mask to remove the absence of gate electrodes and leads, And the photoresist at the position of source and drain electrodes and leads;

After removing the semiconductor layer material where the photoresist is completely exposed, strip the photoresist;

Deposit a passivation layer, pattern the passivation layer and the semiconductor layer, form the drain electrode via hole, and cut off the semiconductor layer connection between adjacent data lines and the semiconductor layer connection between adjacent leads in the edge area;

The array substrate is covered with an indium tin oxide ITO layer, and a patterning process is performed to form a pixel electrode pattern.

After the patterning process is performed on the ITO layer covered on the array substrate, the semiconductor layer connection between the cut off adjacent data lines and the semiconductor layer connection between adjacent lead wires in the edge area are not connected to each other on the covered ITO layer.

The semiconductor layer connection between the cut off adjacent data lines includes: the semiconductor layer connection on the data line crossing the two gate leads, the semiconductor layer connection on the gate lead crossing the two data lines, The semiconductor layer on the common electrode lead passing through the two data lines is connected.

The semiconductor layer is: an amorphous silicon semiconductor layer, an organic semiconductor layer, an oxide semiconductor layer or a low-temperature polysilicon layer.

A thin film field effect transistor TFT structure, comprising: a glass substrate, a gate electrode, a gate insulating layer, a source drain electrode and a semiconductor layer; wherein,

The gate electrode is located on the glass substrate;

The gate insulating layer covers the gate electrode and the glass substrate area not covered by the gate electrode;

The source-drain electrodes are located on the gate insulating layer;

The semiconductor layer covers the source and drain electrodes and the channel region between the source and drain electrodes.

The semiconductor layer is: an amorphous silicon semiconductor layer, an organic semiconductor layer, an oxide semiconductor layer or a low-temperature polysilicon layer.

The method for preparing an array substrate and the TFT structure of the present invention, after preparing source-drain electrodes and lead wires on the gate insulating layer, deposit a semiconductor layer; after coating photoresist, use the gate electrodes, lead wires, and source-drain electrodes on the back of the glass substrate Expose the pattern of electrodes and leads; remove the semiconductor where the photoresist is completely exposed, and then peel off the photoresist; deposit a passivation layer, perform a patterning process on the passivation layer and the semiconductor layer, form a drain electrode via hole, and cut off adjacent data The semiconductor layer connection between the wires and the semiconductor layer connection between the adjacent leads in the edge area; the array substrate is covered with an indium tin oxide ITO layer, and a patterning process is performed to form a pixel electrode pattern. Through the present invention, the carrier can be directly conducted from the source electrode to the drain through the gate insulating layer and the amorphous silicon semiconductor layer during the flow process, without going through the thickness of the amorphous silicon semiconductor layer twice, so that the TFT characteristics can be greatly improved. At the same time, the precise alignment between the semiconductor layer and the source and drain electrodes can still be maintained, and the number of masks used remains unchanged, so that the processing speed can be accelerated, the production capacity can be increased, and the cost can be reduced.

Description of drawings

1 is a schematic cross-sectional view of a TFT device on an array substrate prepared by an amorphous silicon bottom-mounting method;

2 is a schematic flow chart of a method for preparing an array substrate according to the present invention;

3 is a schematic cross-sectional view after the source and drain electrodes are formed;

4 is a schematic cross-sectional view of an amorphous silicon semiconductor layer 5 after deposition;

Figure 5 is a schematic cross-sectional view after coating photoresist;

6 is a schematic cross-sectional view after self-alignment exposure;

7 is a schematic cross-sectional view of amorphous silicon after etching;

Figure 8 is a schematic cross-sectional view after peeling off the photoresist;

FIG. 9 is a schematic cross-sectional view of a TFT on the finally formed array substrate;

FIG. 10 is a schematic structural diagram of the final gate lead;

FIG. 11 is a schematic diagram of the final pixel structure of the array substrate.

Detailed ways

The method for preparing the array substrate proposed by the present invention is mainly based on the electron transport principle at the channel and the back exposure technology. The semiconductor material used in the preparation of the array substrate can be amorphous silicon semiconductor material, organic semiconductor material, oxide semiconductor material or low temperature Polysilicon materials, etc., the method for preparing an array substrate is described below by taking amorphous silicon semiconductor materials as an example. FIG. 2 is a schematic flow chart of a method for preparing an array substrate according to an embodiment of the present invention. As shown in FIG. 2 , the method includes:

Step 201 : after preparing the gate electrode and the lead 3 on the glass substrate 1 , deposit the gate insulating layer 2 .

Step 202 : preparing source-drain electrodes and leads 4 on the deposited gate insulating layer 2 .

A schematic cross-sectional view after the source and drain electrodes are formed is shown in FIG. 3 . In the present invention, the source and drain refer to source and drain.

Step 203: Depositing an amorphous silicon semiconductor layer 5, the amorphous silicon semiconductor layer 5 not only covers the exposed regions of the source and drain electrodes and the gate insulating layer 2, but also fills the channel region between the source and drain electrodes.

A schematic cross-sectional view of the deposited amorphous silicon semiconductor layer 5 is shown in FIG. 4 .

Step 204: Coating photoresist. Here, the photoresist layer 6 covers all areas on the glass substrate.

The cross-sectional schematic diagram after coating the photoresist is shown in FIG. 5 .

Step 205: Use the gate electrode and lead 3 and the patterns of source and drain electrodes and lead 4 to expose the photoresist to a mask on the back of the glass substrate, and remove the parts without the gate electrode and lead 3 and the source and drain electrodes and lead 4 position of photoresist.

Here, the pattern of the gate electrode and the lead 3 and the source-drain electrode and the lead 4 is used for mask exposure to the photoresist, that is: using the pattern of the gate electrode and the lead 3 and the source-drain electrode and the lead 4 as a mask, The photoresist is exposed, and the exposure process belongs to self-parallel exposure. A schematic cross-sectional view after self-alignment exposure is shown in FIG. 6 .

Step 206: performing amorphous silicon etching to remove the amorphous silicon at the photoresist completely exposed position.

A schematic cross-sectional view of amorphous silicon after etching is shown in FIG. 7 .

Step 207: stripping off the photoresist, and preparing a TFT structure topped with amorphous silicon.

A schematic cross-sectional view after peeling off the photoresist is shown in FIG. 8 .

Step 208 : Deposit a passivation layer 8 . Here, the passivation layer 8 covers all areas on the glass substrate 1 .

Step 209: Patterning the passivation layer and the semiconductor layer to form drain electrode via holes, and cutting off the semiconductor layer connection between adjacent data lines and the semiconductor layer connection between adjacent lead wires in the edge region.

The semiconductor layer connection between the cut off adjacent data lines includes but not limited to: the semiconductor layer connection on the data line crossing the two gate leads, the semiconductor layer connection on the gate lead crossing the two data lines Connecting and crossing the semiconductor layer connection on the common electrode lead of the two data lines.

Step 210: covering the array substrate with an ITO layer, and performing a patterning process to form a pixel electrode pattern 9 .

It should be noted that after the patterning process is performed on the ITO layer covered on the array substrate, the semiconductor layer connection between the cut off adjacent data lines and the semiconductor layer connection between adjacent leads in the edge region are covered by the ITO layer. Not connected to each other. In this way, the array substrate is prepared, and then the subsequent processing is carried out according to the traditional process to prepare a TFT-LCD display or an electronic paper display.

The schematic cross-sectional diagram of the TFT on the array substrate formed finally is shown in FIG. 9 , the schematic diagram of the structure of the final gate lead is shown in FIG. 10 , and the schematic diagram of the final pixel structure of the array substrate is shown in FIG. 11 . The sectional structure is the sectional structure shown in FIG. 9 , and the sectional structure obtained along the section line B in FIG. 11 is the sectional structure shown in FIG. 10 .

The present invention also correspondingly proposes a TFT structure, the TFT structure includes: a glass substrate, a gate electrode, a gate insulating layer, a source-drain electrode and a semiconductor layer; wherein,

The gate electrode is located on the glass substrate;

The gate insulating layer covers the gate electrode and the glass substrate area not covered by the gate electrode;

The source-drain electrodes are located on the gate insulating layer;

The semiconductor layer covers the source and drain electrodes and the channel region between the source and drain electrodes.

The semiconductor layer is: an amorphous silicon semiconductor layer, an organic semiconductor layer, an oxide semiconductor layer or a low-temperature polysilicon layer.

It can be seen that compared with the prior art, with the array substrate prepared by the present invention, the carrier can be directly conducted from the source electrode to the drain electrode through the gate insulating layer and the amorphous silicon semiconductor layer during the flow process, without going through two times. The thickness of the amorphous silicon semiconductor layer reduces the influence of amorphous silicon defects on carrier transport, which can greatly improve TFT characteristics, and can still maintain accurate alignment between amorphous silicon and source-drain electrodes, and the number of masks used is not large. changes, thereby improving the characteristics and quality of the product.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.

Claims (6)

1. A method for preparing an array substrate, characterized in that the method comprises: After preparing gate electrodes and leads on the glass substrate, depositing a gate insulating layer; After preparing source and drain electrodes and leads on the gate insulating layer, depositing a semiconductor layer; Coating photoresist on the semiconductor layer, and then using gate electrodes and leads, and patterns of source and drain electrodes and leads on the back of the glass substrate to expose the photoresist to a mask to remove the absence of gate electrodes and leads, And the photoresist at the position of source and drain electrodes and leads; After removing the semiconductor layer material where the photoresist is completely exposed, strip the photoresist; Deposit a passivation layer, pattern the passivation layer and the semiconductor layer, form the drain electrode via hole, and cut off the semiconductor layer connection between adjacent data lines and the semiconductor layer connection between adjacent leads in the edge area; The array substrate is covered with an indium tin oxide ITO layer, and a patterning process is performed to form a pixel electrode pattern. 2. The method according to claim 1, characterized in that, after the patterning process is performed on the ITO layer covered on the array substrate, the connection of the semiconductor layer between the cut off adjacent data lines and the connection between the adjacent leads in the edge area The inter-semiconductor layers are connected to the overlying ITO layers not connected to each other. 3. The method according to claim 1, wherein the semiconductor layer connection between the cut off adjacent data lines comprises: a semiconductor layer connection on a data line crossing two gate leads, crossing The semiconductor layers on the gate leads of the two data lines are connected, and the semiconductor layers on the common electrode leads crossing the two data lines are connected. 4 . The method according to claim 1 , wherein the semiconductor layer is: an amorphous silicon semiconductor layer, an organic semiconductor layer, an oxide semiconductor layer or a low-temperature polysilicon layer. 5. A TFT structure of a thin film field effect transistor, characterized in that, the TFT structure comprises: a glass substrate, a gate electrode, a gate insulating layer, a source-drain electrode and a semiconductor layer; wherein, The gate electrode is located on the glass substrate; The gate insulating layer covers the gate electrode and the glass substrate area not covered by the gate electrode; The source-drain electrodes are located on the gate insulating layer; The semiconductor layer covers the source and drain electrodes and the channel region between the source and drain electrodes. 6 . The TFT structure according to claim 5 , wherein the semiconductor layer is: an amorphous silicon semiconductor layer, an organic semiconductor layer, an oxide semiconductor layer or a low temperature polysilicon layer.

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