CN102325021A - A DPA security evaluation and countermeasure method and its device - Google Patents
A DPA security evaluation and countermeasure method and its device Download PDFInfo
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Abstract
The present invention relates to the crypto chip security fields, especially relate to a kind of DPA fail safe evaluation and test and countercheck and device thereof.The present invention is the basis with chip development instrument, power consumption test instrument and the multiple power consumption leakage analytical model etc. of many levels; Add novel DPA analytical method and countercheck simultaneously; Fit to a cover and adapt to multi-angle, multi-level; Integrate power consumption and sample, reveal the automation platform of analyzing, estimating and resist,, transparent way convenient to try one's best helps the chip designer to carry out objective, rational anti-power consumption capability analysis and evaluation.Therefore, the present invention has following advantage: 1. added in the platform and introduced novel polarity DPA and conversed analysis attack method, can make more reasonably evaluation and test to circuit; 2. platform adds novel KANO countercheck, is the new antagonism mode of providing of user.
Description
Technical field
This patent relates to the crypto chip security fields, especially relates to a kind of DPA fail safe evaluation and test and countercheck and device thereof.
Background technology
Bypass attack (Side Channel Attack) is to rely on the power consumption of revealing in the ciphering process, and physical messages such as time and electromagnetic radiation crack the analysis mode of key.
It is that bypass type is attacked a kind of of (SCA) that DPA (Differential Power Analysis) attacks, and utilizes power consumption and the instruction that is moving, and the relation between the data of carrying out is attacked key.DPA attacks and utilizes digital oscilloscope measuring circuit plate, some power consumption curves of record when encrypting a large amount of clear datas at random, and according to a certain bit division curve group.Correct division will cause producing a peak value on the differential power consumption curve, thereby obtain key, success attack.As one of SCA the most effectively, kind of smart card surplus it has broken through 50 can be widely used in various encryption mechanisms.We have proposed the analytical method of polarity DPA based on original DPA, and polarity DPA is extended in the middle of the conversed analysis.
The power consumption complementary logic is one of present more effective DPA antagonism mode, and existing power consumption complementary logic comprises methods such as SABL, WDDL, DyCML, SDPL, SDRL, DCVSL.DPA attacks for antagonism, and these methods can both reach from bottom eliminates the peak value that DPA attacks, thereby effectively reaches the effect that antagonism DPA attacks.But the shortcoming of power consumption complementary logic is their area.
All be higher than the traditional cmos circuit significantly with power consumption, these methods have also obviously improved design time compared with standard cell circuit in addition.Therefore in practical application, if on complete processor and ASIC, realize these antagonism modes, cost is too expensive, and causes the risk that yields poorly probably.In view of above reason, we improve and have proposed the countercheck of KANO on the basis of WDDL.
Because the existence of bypass attack makes the fail safe of chip be difficult to guarantee that the chip designer need make rational evaluation to the fail safe of chip so.In addition; Add in the process of antagonism at application-specific integrated circuit (ASIC); Because there are differences between the antagonism mode, this just requires cad tools must be able to support to have mixed the somewhat complex design flow process of different-style logic, when improving fail safe; Also must consider aspect problems such as circuit resource and power consumption, so also need a rational evaluation to weigh the relation of fail safe and circuit cost.In view of above reason, just need a unified overall merit framework, comprehensive different simulated environments and suitable index are the chip circuit design of different standards, provide one to estimate accurately.
Summary of the invention
The present invention solves above-mentioned existing in prior technology technical problem; A kind of DPA fail safe evaluation and test and countercheck and device thereof are provided.
Above-mentioned technical problem of the present invention mainly is able to solve through following technical proposals:
A kind of DPA fail safe evaluation and test and countercheck is characterized in that, may further comprise the steps:
Step 1 is carried out system configuration by the system configuration module: comprise component library setting and the tool path setting used in the instrument setting, analytic process of match;
Step 2 is provided with module by parameter and carries out the parameter setting: comprise analysis mode, antagonism mode, performance parameter in the analytical statement and security parameters setting;
Step 3, selected to carry out the setting in power consumption data source according to the user by the Data Source module: according to user's selection, power consumption data is emulated data or measured data;
Step 4 is carried out power consumption analysis and is obtained the corresponding analysis result according to step 1 and the step 2 configuration pin power consumption data source after to completing steps 3 by the power consumption analysis module;
Step 5, carry out analytical statement by analysis module to the analysis result behind the completing steps 4: comprise the data and chart, circuit resource situation, energy mark quantity of power consumption analysis, the reasonability that in group financial statements, provides countercheck is advised.
The present invention is the basis with chip development instrument, power consumption test instrument and the multiple power consumption leakage analytical model etc. of many levels; Add novel DPA analytical method and countercheck simultaneously; Fit to a cover and adapt to multi-angle, multi-level; Integrate power consumption and sample, reveal the automation platform of analyzing, estimating and resist,, transparent way convenient to try one's best helps the chip designer to carry out objective, rational anti-power consumption capability analysis and evaluation.
In above-mentioned a kind of DPA fail safe evaluation and test and countercheck, in the described step 3, the Data Source module comprises simulation unit and actual measurement unit, selects the back to select to carry out following steps according to the user, is emulated data execution in step 3.1 if the user selects power consumption data; If it is measured data execution in step 3.2 that the user selects power consumption data:
Step 3.1; By simulation unit chip circuit is carried out emulation; And obtain corresponding data, and said chip circuit is the design document by user's input, the net table that is generated Verilog by simulation unit is described; Convert the watch circuit description of SPICE net to and be used for circuit simulation through simulation unit then, the said corresponding data that obtains is the emulation power consumption data that obtains behind the circuit simulation;
Step 3.2 is analyzed data with measured data importing actual measurement unit and by the actual measurement unit by the user, and described measured data is test vector file and actual measurement power consumption data file.
In above-mentioned a kind of DPA fail safe evaluation and test and countercheck; Described power consumption analysis module comprises simulation analysis unit and site-test analysis unit; And select to carry out according to user's selection: if the user selects emulated data, the analytical method of then using the user in step 2, to be provided with is directed against emulated data and carries out data analysis; If the user selects measured data, then use the analytical method that is provided with in the step 2 to analyze, the data of said use are the measured datas and corresponding test vector that the user submits to voluntarily.
In above-mentioned a kind of DPA fail safe evaluation and test and countercheck, described simulation analysis unit comprises that original DPA analyzes and polarity DPA analysis, CPA analysis, conversed analysis, User Defined; According to the analytical method that the user selects, carry out and carry out step 4.1 or step 4.2 or step 4.3 or step 4.4 or step 4.5:
Step 4.1, if the user selects original DPA analytical method to carry out data analysis, then operating procedure is following:
Generate the test vector that is used for emulation on A, the platform;
B, carry out circuit power consumption emulation and obtain corresponding emulation power consumption data;
C, user can begin to analyze after importing the test vector file and the power consumption data file of last stage generation and setting the test data outgoing route;
After D, network analysis were accomplished, the user can see success attack institute energy requirement mark quantity, comprised the performance parameter of last stage setting in the circuit resource form, obtained the differential power consumption data in addition, and the chart that the user can observe through image comes the observation data correlation;
Step 4.2, if the user selects polarity DPA analytical method to carry out data analysis, then operating procedure is following:
Generate needed test vector in the phase I power consumption collection earlier in A, the phase I power consumption collection, and the key that needs attack to obtain is set;
B, platform utilize the test vector that generates among the A to carry out phase I power consumption emulation, obtain corresponding power consumption data and carry out corresponding data analysis, obtain corresponding polarity array;
Need to generate this stage power consumption in C, the collection of second stage power consumption and gather needed test vector, and key is set voluntarily, be well-known key here, is changed to entirely 0, can realize through the mode of burning key register in the reality;
D, platform carry out the emulation of second stage power consumption, obtain corresponding data and carry out the corresponding data analysis, obtain corresponding polarity array;
E, utilize the polarity array that two stages obtain, accomplish corresponding attack process and obtain attacking difficulty; Said attack process is exactly the key that polarity array that two stages are obtained is different or obtain attacking, and attacks difficulty and weighs through above-mentioned security parameters setting;
After F, network analysis were accomplished, the user can obtain success attack institute energy requirement mark quantity, comprised the performance parameter of last stage setting in the circuit resource form;
Step 4.3, if the user selects the CPA analytical method to carry out data analysis, then operating procedure is following:
A, user can begin to analyze after importing the test vector file and the power consumption data file of last stage generation and setting the test data outgoing route;
After B, network analysis were accomplished, the user can see success attack institute energy requirement mark quantity, comprised the performance parameter of last stage setting in the circuit resource form, obtained the coefficient correlation data in addition, and the chart that the user can observe through image comes observation data;
The effect that C, internal system will add after the antagonism that access customer sets is analyzed, and in group financial statements, formulates the suggestion of rational counterplan for the user;
Step 4.4, if the user selects the conversed analysis method to carry out data analysis, then operating procedure is following:
A, user can begin to analyze after test vector file and the power consumption data file that imports the last stage generation being set and setting the test data outgoing route;
After B, network analysis finished, the user can observe the S box parameter of reduction, and energy mark quantity and circuit resource statistical conditions;
The effect that C, internal system will add after the antagonism that access customer sets is analyzed, and in group financial statements, formulates the suggestion of rational counterplan for the user;
Step 4.5, if the user selects user self-defining method to carry out data analysis, then operating procedure is following:
A, user submit the code of correlation method voluntarily to; Said code is:
B, the corresponding analytical method of use are carried out data analysis.Does (corresponding analytical method do?)
In above-mentioned a kind of DPA fail safe evaluation and test and countercheck, in the described step 1, the instrument setting comprises: HSPICE, Design Compiler, the setting of HSIM component library comprise: HSPICE, Design Compiler, HSIM corresponding elements storehouse; The tool path setting comprises: the installation path of HSPICE, Design Compiler, HSIM correspondence.
In above-mentioned a kind of DPA fail safe evaluation and test and countercheck, in the described step 2, described antagonism mode comprises: WDDL countercheck, KANO countercheck, user self-defining method; Performance parameter in the analytical statement comprises: circuit resource situation, signal to noise ratio; The security parameters setting comprises: coefficient correlation, conditional entropy and mutual information, energy mark quantity.
A kind of device that uses DPA fail safe evaluation and test and countercheck; It is characterized in that; Comprise that the system configuration module, the parameter that link to each other successively are provided with module, Data Source module, power consumption analysis module and analysis module; Said Data Source module comprises simulation unit and actual measurement unit, and said power consumption analysis module comprises simulation analysis unit and site-test analysis unit.
Therefore, the present invention has following advantage: 1. added in the platform and introduced novel polarity DPA and conversed analysis attack method, can make more reasonably evaluation and test to circuit; 2. platform adds novel KANO countercheck, is the new antagonism mode of providing of user; 3. platform has decidability and intelligent, and platform accumulates the analysis experience when different pieces of information is analyzed in the use of varying environment, and constantly the analysis ability of lifting platform self better realizes intelligent; 4. through a uniform platform, to multiple different ciphers circuit design and towards multiple attack method and countercheck; 5. platform has the convenience characteristics of operation, and platform has upgradability in addition, all customizable and upgrading of the attack method in the platform, countercheck, evaluation index.
Description of drawings
Fig. 1 representes the overall system frame diagram;
Fig. 2 representes original DPA simulation analysis flow chart;
Fig. 3 representes polarity DPA simulation analysis flow chart.
Embodiment
Pass through embodiment below, and combine accompanying drawing, do further bright specifically technical scheme of the present invention.
Embodiment:
A kind of DPA fail safe evaluation and test and countercheck may further comprise the steps:
Step 1 is carried out system configuration by the system configuration module: comprise component library setting and the tool path setting used in the instrument setting, analytic process of match; The instrument setting comprises: HSPICE, Design Compiler, the setting of HSIM component library comprise: HSPICE, Design Compiler, HSIM corresponding elements storehouse; The tool path setting comprises: the installation path of HSPICE, Design Compiler, HSIM correspondence; The antagonism mode comprises: WDDL countercheck, KANO countercheck, user self-defining method; Performance parameter in the analytical statement comprises: circuit resource situation, signal to noise ratio; The security parameters setting comprises: coefficient correlation, conditional entropy and mutual information, energy mark quantity.
Step 2 is provided with module by parameter and carries out the parameter setting: comprise analysis mode, antagonism mode, performance parameter in the analytical statement and security parameters setting;
Step 3, selected to carry out the setting in power consumption data source according to the user by the Data Source module: according to user's selection, power consumption data is emulated data or measured data; The Data Source module comprises simulation unit and actual measurement unit, selects the back to select to carry out following steps according to the user, is emulated data execution in step 3.1 if the user selects power consumption data; If it is measured data execution in step 3.2 that the user selects power consumption data:
Step 3.1; By simulation unit chip circuit is carried out emulation; And obtain corresponding data, and said chip circuit is the design document by user's input, the net table that is generated Verilog by simulation unit is described; Convert the watch circuit description of SPICE net to and be used for circuit simulation through simulation unit then, the said corresponding data that obtains is the emulation power consumption data that obtains behind the circuit simulation;
Step 3.2 is analyzed data with measured data importing actual measurement unit and by the actual measurement unit by the user, and described measured data is test vector file and actual measurement power consumption data file.
Step 4 is carried out power consumption analysis and is obtained the corresponding analysis result according to step 1 and the step 2 configuration pin power consumption data source after to completing steps 3 by the power consumption analysis module; The power consumption analysis module comprises simulation analysis unit and site-test analysis unit, and selects to carry out according to user's selection: if the user selects emulated data, the analytical method of then using the user in step 2, to be provided with is carried out data analysis to emulated data; If the user selects measured data, then use the analytical method that is provided with in the step 2 to analyze, the data of said use are the measured datas and corresponding test vector that the user submits to voluntarily.
The simulation analysis unit comprises that original DPA analyzes and polarity DPA analysis, CPA analysis, conversed analysis, User Defined; According to the analytical method that the user selects, carry out and carry out step 4.1 or step 4.2,4.3,4.4,4.5:
Step 4.1, if the user selects original DPA analytical method to carry out data analysis, then operating procedure is following:
Generate the test vector that is used for emulation on D, the platform;
E, carry out circuit power consumption emulation and obtain corresponding emulation power consumption data;
F, user can begin to analyze after importing the test vector file and the power consumption data file of last stage generation and setting the test data outgoing route;
After D, network analysis were accomplished, the user can see success attack institute energy requirement mark quantity, comprised the performance parameter of last stage setting in the circuit resource form, obtained the differential power consumption data in addition, and the chart that the user can observe through image comes the observation data correlation;
Step 4.2, if the user selects polarity DPA analytical method to carry out data analysis, then operating procedure is following:
Generate needed test vector in the phase I power consumption collection earlier in G, the phase I power consumption collection, and the key that needs attack to obtain is set;
H, platform utilize the test vector that generates among the A to carry out phase I power consumption emulation, obtain corresponding power consumption data and carry out corresponding data analysis, obtain corresponding polarity array;
Need to generate this stage power consumption in I, the collection of second stage power consumption and gather needed test vector, and key is set voluntarily, be well-known key here, is changed to entirely 0, can realize through the mode of burning key register in the reality;
J, platform carry out the emulation of second stage power consumption, obtain corresponding data and carry out the corresponding data analysis, obtain corresponding polarity array;
K, utilize the polarity array that two stages obtain, accomplish corresponding attack process and obtain attacking difficulty; Said attack process is exactly the key that polarity array that two stages are obtained is different or obtain attacking, and attacks difficulty and weighs through above-mentioned security parameters setting;
After L, network analysis were accomplished, the user can obtain success attack institute energy requirement mark quantity, comprised the performance parameter of last stage setting in the circuit resource form;
Step 4.3, if the user selects the CPA analytical method to carry out data analysis, then operating procedure is following:
D, user can begin to analyze after importing the test vector file and the power consumption data file of last stage generation and setting the test data outgoing route;
After E, network analysis were accomplished, the user can see success attack institute energy requirement mark quantity, comprised the performance parameter of last stage setting in the circuit resource form, obtained the coefficient correlation data in addition, and the chart that the user can observe through image comes observation data;
The effect that F, internal system will add after the antagonism that access customer sets is analyzed, and in group financial statements, formulates the suggestion of rational counterplan for the user;
Step 4.4, if the user selects the conversed analysis method to carry out data analysis, then operating procedure is following:
D, user can begin to analyze after test vector file and the power consumption data file that imports the last stage generation being set and setting the test data outgoing route;
After E, network analysis finished, the user can observe the S box parameter of reduction, and energy mark quantity and circuit resource statistical conditions;
The effect that F, internal system will add after the antagonism that access customer sets is analyzed, and in group financial statements, formulates the suggestion of rational counterplan for the user;
Step 4.5, if the user selects user self-defining method to carry out data analysis, then operating procedure is following:
A. the user submits the code of corresponding analysis method voluntarily to; Said code is: use programming language identical with making platform or compatible mutually programming language, like c#, java etc. write the program code of the analytical method of user oneself definition;
B. use corresponding analytical method to carry out data analysis, institute's corresponding analytical method in family is the described analytical method of program language that the user submits in the steps A.
Step 5, carry out analytical statement by analysis module to the analysis result behind the completing steps 4: comprise the data and chart, circuit resource situation, energy mark quantity of power consumption analysis, the reasonability that in group financial statements, provides countercheck is advised; Countercheck is in analytic process, to add, and contrasts with former design, draws the best antagonism mode in the countercheck.
Specific embodiment described herein only is that the present invention's spirit is illustrated.Person of ordinary skill in the field of the present invention can make various modifications or replenishes or adopt similar mode to substitute described specific embodiment, but can't depart from spirit of the present invention or surmount the defined scope of appended claims.
Although this paper has used system configuration module, parameter that terms such as module, Data Source module, power consumption analysis module, analysis module, simulation unit, actual measurement unit, simulation analysis unit, site-test analysis unit are set morely, do not get rid of the possibility of using other term.Using these terms only is in order to describe and explain essence of the present invention more easily; It all is contrary with spirit of the present invention being construed to any additional restriction to them.
Claims (7)
1. DPA fail safe evaluation and test and countercheck is characterized in that, may further comprise the steps:
Step 1 is carried out system configuration by the system configuration module: comprise component library setting and the tool path setting used in the instrument setting, analytic process of match;
Step 2 is provided with module by parameter and carries out the parameter setting: comprise analysis mode, antagonism mode, performance parameter in the analytical statement and security parameters setting;
Step 3, selected to carry out the setting in power consumption data source according to the user by the Data Source module: according to user's selection, power consumption data is emulated data or measured data;
Step 4 is carried out power consumption analysis and is obtained the corresponding analysis result according to step 1 and the step 2 configuration pin power consumption data source after to completing steps 3 by the power consumption analysis module;
Step 5, carry out analytical statement by analysis module to the analysis result behind the completing steps 4: comprise the data and chart, circuit resource situation, energy mark quantity of power consumption analysis, the reasonability that in group financial statements, provides countercheck is advised.
2. a kind of DPA fail safe evaluation and test according to claim 1 and countercheck; It is characterized in that; In the described step 3; The Data Source module comprises simulation unit and actual measurement unit, selects the back to select to carry out following steps according to the user, is emulated data execution in step 3.1 if the user selects power consumption data; If it is measured data execution in step 3.2 that the user selects power consumption data:
Step 3.1; By simulation unit chip circuit is carried out emulation; And obtain corresponding data, and said chip circuit is the design document by user's input, the net table that is generated Verilog by simulation unit is described; Convert the watch circuit description of SPICE net to and be used for circuit simulation through simulation unit then, the said corresponding data that obtains is the emulation power consumption data that obtains behind the circuit simulation;
Step 3.2 is analyzed data with measured data importing actual measurement unit and by the actual measurement unit by the user, and described measured data is test vector file and actual measurement power consumption data file.
3. a kind of DPA fail safe evaluation and test according to claim 1 and countercheck; It is characterized in that; Described power consumption analysis module comprises simulation analysis unit and site-test analysis unit; And select to carry out according to user's selection: if the user selects emulated data, the analytical method of then using the user in step 2, to be provided with is directed against emulated data and carries out data analysis; If the user selects measured data, then use the analytical method that is provided with in the step 2 to analyze, the data of said use are the measured datas and corresponding test vector that the user submits to voluntarily.
4. a kind of DPA fail safe evaluation and test according to claim 3 and countercheck is characterized in that, described simulation analysis unit comprises that original DPA analyzes and polarity DPA analysis, CPA analysis, conversed analysis, User Defined; According to the analytical method that the user selects, carry out and carry out step 4.1 or step 4.2 or step 4.3 or step 4.4 or step 4.5:
Step 4.1, if the user selects original DPA analytical method to carry out data analysis, then operating procedure is following:
Generate the test vector that is used for emulation on the platform;
Carry out circuit power consumption emulation and obtain corresponding emulation power consumption data;
The user can begin to analyze after importing the test vector file and the power consumption data file of last stage generation and setting the test data outgoing route;
After D, network analysis were accomplished, the user can see success attack institute energy requirement mark quantity, comprised the performance parameter of last stage setting in the circuit resource form, obtained the differential power consumption data in addition, and the chart that the user can observe through image comes the observation data correlation;
Step 4.2, if the user selects polarity DPA analytical method to carry out data analysis, then operating procedure is following:
Generate needed test vector in the phase I power consumption collection earlier in A, the phase I power consumption collection, and the key that needs attack to obtain is set;
B, platform utilize the test vector that generates among the A to carry out phase I power consumption emulation, obtain corresponding power consumption data and carry out corresponding data analysis, obtain corresponding polarity array;
Need to generate this stage power consumption in C, the collection of second stage power consumption and gather needed test vector, and key is set voluntarily, be well-known key here, is changed to entirely 0, can realize through the mode of burning key register in the reality;
D, platform carry out the emulation of second stage power consumption, obtain corresponding data and carry out the corresponding data analysis, obtain corresponding polarity array;
E, utilize the polarity array that two stages obtain, accomplish corresponding attack process and obtain attacking difficulty; Said attack process is exactly the key that polarity array that two stages are obtained is different or obtain attacking, and attacks difficulty and weighs through above-mentioned security parameters setting;
After F, network analysis were accomplished, the user can obtain success attack institute energy requirement mark quantity, comprised the performance parameter of last stage setting in the circuit resource form;
Step 4.3, if the user selects the CPA analytical method to carry out data analysis, then operating procedure is following:
A, user can begin to analyze after importing the test vector file and the power consumption data file of last stage generation and setting the test data outgoing route;
After B, network analysis were accomplished, the user can see success attack institute energy requirement mark quantity, comprised the performance parameter of last stage setting in the circuit resource form, obtained the coefficient correlation data in addition, and the chart that the user can observe through image comes observation data;
The effect that C, internal system will add after the antagonism that access customer sets is analyzed, and in group financial statements, formulates the suggestion of rational counterplan for the user;
Step 4.4, if the user selects the conversed analysis method to carry out data analysis, then operating procedure is following:
A, user can begin to analyze after test vector file and the power consumption data file that imports the last stage generation being set and setting the test data outgoing route;
After B, network analysis finished, the user can observe the S box parameter of reduction, and energy mark quantity and circuit resource statistical conditions;
The effect that C, internal system will add after the antagonism that access customer sets is analyzed, and in group financial statements, formulates the suggestion of rational counterplan for the user;
Step 4.5, if the user selects user self-defining method to carry out data analysis, then operating procedure is following:
A, user submit the code of corresponding analysis method voluntarily to; Said code is: use programming language identical with making platform or compatible mutually programming language, write the program code of the analytical method of user oneself definition;
B, the corresponding analytical method of use are carried out data analysis, and corresponding analytical method is to be the described analytical method of program language that the user submits in the steps A.
5. a kind of DPA fail safe evaluation and test according to claim 1 and countercheck; It is characterized in that; In the described step 1, the instrument setting comprises: HSPICE, Design Compiler, the setting of HSIM component library comprise: HSPICE, Design Compiler, HSIM corresponding elements storehouse; The tool path setting comprises: the installation path of HSPICE, Design Compiler, HSIM correspondence.
6. a kind of DPA fail safe evaluation and test according to claim 1 and countercheck is characterized in that, in the described step 2, described antagonism mode comprises: WDDL countercheck, KANO countercheck, user self-defining method; Performance parameter in the analytical statement comprises: circuit resource situation, signal to noise ratio; The security parameters setting comprises: coefficient correlation, conditional entropy and mutual information, energy mark quantity.
7. device that uses claim 1 described DPA fail safe evaluation and test and countercheck; It is characterized in that; Comprise that the system configuration module, the parameter that link to each other successively are provided with module, Data Source module, power consumption analysis module and analysis module; Said Data Source module comprises simulation unit and actual measurement unit, and said power consumption analysis module comprises simulation analysis unit and site-test analysis unit.
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| CN103888242B (en) * | 2014-03-31 | 2017-03-29 | 武汉大学 | A kind of intelligent cipher system towards side Multiple Channel Analysis |
| CN106096177A (en) * | 2016-06-23 | 2016-11-09 | 中国电子科技集团公司第五十八研究所 | A kind of multi-chip joint simulation method based on traditional EDA instrument |
| CN112134685A (en) * | 2020-10-27 | 2020-12-25 | 深圳安捷丽新技术有限公司 | DPA attack prevention to-be-tested circuit security simulation analysis method and device |
| CN112134685B (en) * | 2020-10-27 | 2024-02-13 | 深圳安捷丽新技术有限公司 | DPA attack-preventing circuit to be tested safety simulation analysis method and device |
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