CN102035641A - Device and method for implementing AES encryption and decryption - Google Patents
Device and method for implementing AES encryption and decryption Download PDFInfo
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- H—ELECTRICITY
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- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
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Abstract
The invention provides a device and a method for implementing AES (advanced encryption standard) encryption and decryption. The method comprises the following steps of: receiving data to be encrypted or decrypted, and copying the data to be encrypted or decrypted into a state matrix; adding the state matrix and an initial key; performing Nr-1 round transformation on the state matrix added with the initial key; and performing incomplete round transformation on the state matrix subjected to Nr-1 round transformation so as to complete the encryption or decryption processing, wherein Nr is the round number required by encryption and decryption. The invention provides a device and a method for implementing AES encryption and AES decryption; meanwhile, the circuit scale can be greatly reduced.
Description
Technical field
The invention belongs to the encryption and decryption technology field, specifically, relate to the apparatus and method of a kind of realization AES (Advanced Encryption Standard, Advanced Encryption Standard) enciphering and deciphering algorithm.
Background technology
Along with network technology, the communication technology and development of multimedia technology, be that the information technology of representative has been penetrated in the middle of the daily life fully with the Internet, mobile communication.Thing followed information security issue becomes the problem that people press for solution.Information security need rely on security mechanism to finish, and security mechanism mainly depends on cryptographic technique, and cryptographic technique is the core technology of information security.Employing safely, cryptographic algorithm is the key that ensures information security efficiently, and therefore the research to cryptographic algorithm and realization thereof has very strong practical significance.
American National Standard and technical research institute (NIST) have formally announced new standard AES November 26 calendar year 2001, and for a cryptographic algorithm, safety and performance are two most important aspects.By special algorithm design, aes algorithm has solved the des encryption algorithm and has been attacked the leak of appearance, and up to now, aes algorithm does not also have known leak.Aes algorithm can be widely used in the various products, for improving product competitiveness important meaning is arranged.
AES just begins formally effective on May 26th, 2002, therefore now still be in the period that new and old encryption standard substitutes, and present being seen aes algorithm hardware mainly is to realize testability or experimental application.Domestic research and application facet in cryptographic algorithm started late, be subjected to the restriction of various conditions in addition again, research to AES mainly concentrates on aes algorithm itself, aspect only algorithm realizations, major part is that software is realized, along with aes algorithm gets more and more people's extensive concerning day by day, will rise steadily to the demand of hard-wired AES product.
Aes algorithm comprises 4 steps: byte is replaced, the row displacement, and the row mixing transformation, round key adds.Wherein the realization of byte replacement generally is to use look-up tables'implementation.Using the look-up tables'implementation byte replaces and need come store look-up tables by a large amount of hardware resources.For instance, AES encryption and decryption for 128 bits, 128 Bit datas are totally 16 bytes, encryption and decryption all need to use 16 substitution tables respectively when carrying out linear transformation, also need to use 4 substitution tables at the round key expansion in addition, need use 36 forms so altogether, 256 bytes of every form coexistence storage, these forms of storage need the space of 9KB altogether like this, and this is a huge hardware spending.And, can't realize resource-sharing because the look-up table of encrypting is different with the look-up table of deciphering.
Therefore, how to realize the hardware of the AES nuclear of practical application in related network and the multimedia system, and make it have the advantages that to save hardware resource, become the problem that the technical staff need consider.
Summary of the invention
Technical problem to be solved by this invention provides a kind of apparatus and method of the AES of realization encryption and decryption, can realize the computing of AES encryption and decryption, and can the economize on hardware resource.
In order to solve the problems of the technologies described above, the invention provides a kind of method of the AES of realization encryption and decryption, comprising:
Receive to be encrypted or treat data decryption, with to be encrypted or treat that data decryption copies in the middle of the state matrix;
With state matrix and initial key addition;
To pass through Nr-l round transformation with the state matrix after the initial key addition;
To carrying out an incomplete round transformation, encrypt or decryption processing thereby finish through the state matrix behind Nr-l the round transformation;
Wherein, Nr is for encrypting and required wheel number during deciphering.
In order to solve the problems of the technologies described above, the present invention also provides a kind of device of the AES of realization encryption and decryption, comprising:
Processor interface is used for the input and output data;
Receive the first-in first-out unit, link to each other, be used to receive to be encrypted or decrypted data, and send AES encryption and decryption nuclear to described processor interface;
AES encryption and decryption nuclear is used for that the data that read from reception first-in first-out unit are carried out encryption and decryption and handles;
Send the first-in first-out unit, be used for encrypt or decryption processing after data send to processor interface;
The direct memory access channel interface, be used for producing direct memory access channel read-write requests signal, remove the direct memory access channel read-write requests after receiving direct memory access channel read-write requests response signal according to the state that receives the first-in first-out unit and send the first-in first-out unit.
The invention provides a kind of AES that both can realize and encrypt, can realize the apparatus and method of AES deciphering again, can reduce the scale of circuit simultaneously again greatly.Realize the byte replacement by on the Jia Luohua territory, carrying out inversion operation and affine transformation, can save the hardware resource of a large amount of store look-up tables, reduce the scale of circuit greatly.
Description of drawings
Fig. 1 is Nb of the present invention, Nk and Nr mapping table;
Fig. 2 is an AES cryptographic algorithm flow chart of the present invention;
Fig. 3 is an AES decipherment algorithm flow chart of the present invention;
Fig. 4 is an AES equivalence deciphering algorithm flow chart of the present invention;
Fig. 5 is an AES ciphering and deciphering device block diagram of the present invention;
Fig. 6 is an AES encryption and decryption nuclear block diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing to a preferred embodiment of the present invention will be described in detail.
Rijndael (Lai En Dell) algorithm is the block encryption algorithm with variable packet length and changeable key length, the arbitrary integer that its block length and key length all can be set at 32 bits independently doubly, minimum value is 128 bits, maximum is 256 bits, be that data length and key length all can be 128 bits, 192 bits and 256 bits.
AES is actual to be the special case of Rijndael, in its codes and standards, clearly defined data packet length and be fixed as 128 bits, and key length can be 128 bits, 192 bits or 256 bits are called " AES 1 ", " AES 1 " and " AES 1 ".The present invention is that example is described with " AES 1 ".
The input of AES, to can be regarded as with the byte be the one-dimension array of unit in output.Be called state in the median that adds, data processing obtains in the decrypting process, because state table is shown as the form of matrix, so be called state matrix again.The columns of the state matrix that each packet forms is designated as Nb, and its value equals block length divided by 32, and for AES, Nb is fixed as 4.Similarly, it is the matrix form of unit that the key grouping also is expressed as with the byte, and this matrix column number scale is Nk.Because key length can be 128,192 or 256, so Nk can value 4,6 or 8.Nr represents to add, required wheel number when deciphering.For AES, according to the key length difference, but Nr value 10,12 or 14.Nb, the corresponding relation of Nk and Nr as shown in Figure 1.
Aes algorithm is when encryption and decryption, and basic arithmetic unit is a round transformation, and each round transformation comprises four different operating steps, all is unit with the byte to the operation of data.
When handling the data of a grouping, may further comprise the steps:
Step 101: with initial to be encrypted or treat that data decryption copies in the middle of the state matrix;
Step 102: with state matrix and initial key addition;
Step 103: will pass through (Nr-l) individual round transformation with the state matrix after the initial key addition;
Step 104: the state matrix behind process (Nr-l) individual round transformation is carried out an incomplete round transformation, thereby entire process is finished.
Wherein, each round transformation comprises four operating procedure: SubBytes (byte replacement), shiftRows (row displacement), MixColumns (row mix) and AddRoundKey (round key adds).
Wherein three steps have description in shiftRows (row displacement), MixColumns (row mix) and AddRoundKey (round key adds) prior art.
In addition, incomplete round transformation described in the step 104, be meant the round transformation that has omitted MixColumns (row mix) conversion, promptly incomplete round transformation only comprises SubBytes (byte replacement), shiftRows (row displacement) and three operating procedures of AddRoundKey (round key adds).
It is pointed out that Fig. 2 and Fig. 3 among the present invention take turns with 10 to be example, may be other numerical value in the practical application, such as may being 12 or 14.
With the ciphering process is example, with reference to shown in Figure 2, is AES cryptographic algorithm flow chart of the present invention.Described AES cryptographic algorithm comprises: in the present embodiment, be that the clear data with 128 bits is that example is described.
Step 201: receive 128 bits clear data to be encrypted;
Step 202: with data to be encrypted and initial key addition;
Step 203: the state matrix after the initial key addition through (Nr-l) individual round transformation, when carrying out (Nr-l) individual round transformation, is arrived round key (Nr-l) addition with round key 1 successively;
Step 204: to carrying out an incomplete round transformation through the state matrix behind (Nr-l) individual round transformation, thereby entire process finish, obtain 128 bit ciphertexts.
Because AES is a symmetry algorithm, so all utilize the inverse transformation of encryption just to obtain understanding close algorithm the conversion of ciphering process contrary operation and each step.Corresponding four calculation step of encrypting, decrypting process are called InvsubBytes (contrary byte is replaced), InvshiftRows (displacement of driving in the wrong direction), InvMixCloumns (contrary row mix) and InvAddRoundKey (contrary round key adds).Because it all is to carry out XOR that the key of encryption and decryption adds, so the InvAddRoundKey of decrypting process is identical with AddRoundKey in the ciphering process.Backward when the round key of participation computing is encryption in proper order in the decrypting process.
The flow process of whole decrypt operation process may further comprise the steps as shown in Figure 3:
Step 301: receive 128 bits encrypt data to be deciphered;
Step 302: the Nr round key addition in the time of will treating decrypted data and encrypt;
Step 303: the state matrix after will the Nr round key addition when encrypting is through (Nr-l) individual round transformation, when carrying out (Nr-l) individual round transformation, successively with round key (Nr-l) to round key 1 addition;
Step 304: to carrying out an incomplete round transformation through the state matrix behind (Nr-l) individual round transformation, thereby and finish with initial key addition entire process, obtain 128 bit clear datas.
When adopting this direct decipherment algorithm, encryption and decryption differ greatly on the computing flow process, and this can cause the increase of hardware design complexity.Yet the characteristic of aes algorithm makes that encryption and decryption just can have identical computing flow process by the simple equivalent conversion, and each conversion when wherein deciphering is the inverse transformation of encrypting correspondent transform, and the flow process of equivalence deciphering calculating process as shown in Figure 4.
Step 401: receive 128 bits encrypt data to be deciphered;
Step 402: the Nr round key addition in the time of will treating decrypted data and encrypt;
Step 403: the state matrix after will the Nr round key addition when encrypting is through (Nr-l) individual round transformation, when carrying out (Nr-l) individual round transformation, successively with round key (Nr-l) to round key 1 through addition behind the reverse row mixing transformation;
Step 404: to carrying out an incomplete round transformation through the state matrix behind (Nr-l) individual round transformation, thereby and finish with initial key addition entire process, obtain 128 bit clear datas.
AddRoundKey carries out XOR exactly, and shiftRows and InvshiffRows, MixColumns and InvMixCloumns are also fairly simple, are not described in detail at this.Introduce the implementation method of SubByte and InvSubByte below.If the computing of using on the Jia Luohua territory realizes that during encryption, byte is replaced and is divided into following two steps: the first step, each table of bytes is shown as its form on finite field gf (256), obtain the multiplicative inverse of this byte afterwards; In second step, the multiplicative inverse of trying to achieve is carried out an affine transformation.During deciphering, contrary byte is replaced and is divided into following two steps: the first step, the multiplicative inverse of trying to achieve is carried out a contrary affine transformation; In second step, each table of bytes is shown as it obtains this byte after the form on the finite field gf (256) multiplicative inverse.
By above analysis as can be seen, the something in common of SubBytes and InvsubBytes conversion is all need ask the multiplicative inverse of waiting to replace byte on finite field, and difference is to ask affine transformation or contrary affine transformation.For multiplicative inverse,, can earlier the element on the GF (256) be transformed on the GF (16) because GF (256) can be regarded as the expansion of GF (16), ask its inverse element (calculating simple) then, again with the inverse element of trying to achieve, carry out conversion at last, obtain the result on the GF (256).
Fig. 5 is the ciphering and deciphering device block diagram of AES of the present invention.It comprises CPU (processor) interface 50, receives FIFO (First-In First-Out, first-in first-out) Unit 51, sends FIFO Unit 52, AES encryption and decryption nuclear 53, and DMA (Direct Memory Access, direct memory access channel) interface 54.
Cpu i/f 50 is used for register is configured, the input and output data; The initial key of this register configuration algorithm is encrypted still deciphering etc.;
Receive the FIFO51 unit, link to each other, be used to receive to be encrypted or decrypted data, and send AES encryption and decryption nuclear to described cpu i/f;
AES encryption and decryption nuclear 53 is used for that the data that read from reception cell fifo 51 are carried out encryption and decryption and handles;
Send the FIFO52 unit, be used for encrypt or decryption processing after data send to cpu i/f 50;
The data for the treatment of encryption and decryption are input in the reception cell fifo 51 by the CPU50 bus, AES encryption and decryption nuclear 53 carries out encryption and decryption from the data that reception cell fifo 51 reads 128 bit bit wides, after handling the result is write in the transmission cell fifo 52, export by cpu bus at last.Receiving cell fifo 51 and sending cell fifo 52 is 2 asymmetric FIFO, towards one side data width 32 bits of CPU50 interface, is 128 bits towards a data bit width of AES encryption and decryption nuclear 53.DMA interface 54 produces DMA read-write requests signal according to the state that receives cell fifo 51 and send cell fifo 52, removes the DMA read-write requests after receiving DMA read-write requests response signal.
Fig. 6 is an AES encryption and decryption nuclear block diagram of the present invention.AES encryption and decryption nuclear 53 comprises key expansion unit 531, algorithm controls unit 532, row displacement and byte converter unit 533 and row mixing transformation unit 534.
Row displacement and byte converter unit 533 are used for capable displacement of described first transform data and byte conversion are exported second transform data to row mixing transformation unit 534 and algorithm controls unit 532;
Row mixing transformation unit 534 is used to receive described second transform data, and exports the 3rd transform data to algorithm controls unit 532.
Specifically, key expansion unit 531 is used to generate each and takes turns required key, carries out cipher key spreading, and cipher key spreading is carried out when algorithm initialization, and the circulation key is stored among the RAM (Random Access Memory is random access memory); Algorithm controls unit 532 is used to control the described circulation key output that is stored in a RAM and uses.Wherein the byte in the cipher key spreading is replaced and is also used above-mentioned computational methods to carry out.The data for the treatment of encryption and decryption are input in the algorithm controls unit 532, by algorithm controls unit 532 control aes algorithm processes, export the data after the encryption and decryption at last.Algorithm controls unit 532 each intermediate object program of taking turns of output are that transform data 1 is to row displacement and byte converter unit 533, go and be shifted and the byte conversion, transform data 2 outputs to row mixing transformation unit 534 as a result, row mixing transformation unit 534 is used to carry out the row mixing transformation, obtain transform data 3, transform data 2 and transform data 3 all output in the algorithm controls unit 532 to carry out the next round computing.Last transform data of taking turns 1 is exactly final result, just the data after the encryption and decryption.
The present invention can realize the encryption and decryption of AES, replaces by adopting Calculation Method to carry out byte, and the maximized common source of encryption and decryption has reduced circuit scale greatly, can be widely used in related network and the multimedia system.
It is pointed out that the above only is preferred embodiment of the present invention, is not to be used for limiting practical range of the present invention, and every variation and modification according to the equivalence that the present invention did are all covered by claim of the present invention.
Claims (9)
1. a method that realizes the AES encryption and decryption is characterized in that, comprising:
Receive to be encrypted or treat data decryption, with to be encrypted or treat that data decryption copies in the middle of the state matrix;
With state matrix and initial key addition;
To pass through Nr-l round transformation with the state matrix after the initial key addition;
To carrying out an incomplete round transformation, encrypt or decryption processing thereby finish through the state matrix behind Nr-l the round transformation;
Wherein, Nr is for encrypting and required wheel number during deciphering.
2. the method for claim 1 is characterized in that, described round transformation comprises:
Carry out the byte replacement operation, go shifting function, carry out the row married operation, carry out the round key add operation;
Described incomplete round transformation comprises: carry out the byte replacement operation, go shifting function, carry out the round key add operation.
3. method as claimed in claim 2 is characterized in that, the described byte replacement operation that carries out when encrypting, comprising:
Each table of bytes is shown as its form on finite field gf 256, obtains the multiplicative inverse of this byte afterwards;
The multiplicative inverse of trying to achieve is carried out an affine transformation.
4. method as claimed in claim 2 is characterized in that, the described byte replacement operation that carries out when being decrypted, comprising:
The multiplicative inverse of trying to achieve is carried out a contrary affine transformation;
Each table of bytes is shown as its form on finite field gf 256, obtains the multiplicative inverse of this byte afterwards.
5. as claim 3 or 4 described methods, it is characterized in that, described each table of bytes be shown as its form on finite field gf 256, obtain the multiplicative inverse of this byte afterwards, comprising:
Earlier the element on the GF256 is transformed on the GF16, asks its inverse element then,, carry out conversion, obtain the result on the GF256 at last again with the inverse element of trying to achieve.
6. the method for claim 1 is characterized in that, and is described with Nr-l round transformation of the process of the state matrix after the initial key addition, when encrypting, comprising:
When carrying out Nr-l round transformation, arrive round key Nr-l addition with round key 1 successively.
7. the method for claim 1 is characterized in that, and is described with Nr-l round transformation of the process of the state matrix after the initial key addition, when being decrypted, comprising:
When carrying out Nr-l round transformation, successively with round key Nr-l to round key 1 addition.
8. a device of realizing the AES encryption and decryption is characterized in that, comprising:
Processor interface is used for the input and output data;
Receive the first-in first-out unit, link to each other, be used to receive to be encrypted or decrypted data, and send AES encryption and decryption nuclear to described processor interface;
AES encryption and decryption nuclear is used for that the data that read from reception first-in first-out unit are carried out encryption and decryption and handles;
Send the first-in first-out unit, be used for encrypt or decryption processing after data send to processor interface;
The direct memory access channel interface, be used for producing direct memory access channel read-write requests signal, remove the direct memory access channel read-write requests after receiving direct memory access channel read-write requests response signal according to the state that receives the first-in first-out unit and send the first-in first-out unit.
9. device as claimed in claim 8 is characterized in that, described AES encryption and decryption nuclear comprises:
Key expansion unit is used to generate each and takes turns required key;
The algorithm controls unit is used for Control Circulation key output and uses, and export each intermediate object program of taking turns promptly first transform data and be used to export the data of last first transform data of taking turns after to row displacement and byte converter unit as encryption and decryption;
Row displacement and byte converter unit are used for capable displacement of described first transform data and byte conversion, export second transform data to row mixing transformation unit and the algorithm controls unit;
Row mixing transformation unit is used to receive described second transform data, and exports the 3rd transform data to the algorithm controls unit.
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| CN2009101784104A CN102035641A (en) | 2009-09-24 | 2009-09-24 | Device and method for implementing AES encryption and decryption |
| PCT/CN2010/073455 WO2010145451A1 (en) | 2009-09-24 | 2010-06-02 | Device and method for implementing advanced encryption standard (aes) encryption and dencryption |
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| CN2009101784104A CN102035641A (en) | 2009-09-24 | 2009-09-24 | Device and method for implementing AES encryption and decryption |
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| CN102664729A (en) * | 2012-04-28 | 2012-09-12 | 中山大学 | Field programmable gate array (FPGA)-based advanced encryption standard (AES) encryption and decryption network communication device and implementation method thereof |
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| CN1677921A (en) * | 2004-03-31 | 2005-10-05 | 华为技术有限公司 | The Method of Realizing Data Encryption Through Programmable Device |
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