CN101853852A - Groove MOS (Metal Oxide Semiconductor) device integrating Schottky diodes in unit cell and manufacture method - Google Patents
Groove MOS (Metal Oxide Semiconductor) device integrating Schottky diodes in unit cell and manufacture method Download PDFInfo
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Abstract
The invention relates to a groove MOS (Metal Oxide Semiconductor) device integrating Schottky diodes in a unit cell and a manufacture method. In the method, the Schottky diodes are technically integrated in each groove MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) unit cell, and an N+source electrode ohmic contact of the MOSFET, an ohmic contact of a P-shaped well and anode contacts of the Schottky diodes commonly use a same contact hole, thereby efficiently saving the area of the silicon surface and lowering the chip cost. On the aspect of manufacture technology, the invention does not need an additional photomask or a photoetching step, but introduces an easily controlled medium side wall and a self-aligned technology and can also obtain the groove MOSFET device with low cost, simple processing steps, high performance and high reliability.
Description
Technical field
The present invention relates to a kind of large-power MOS part and manufacture method thereof, particularly the groove MOS device of integrated schottky diode and manufacture method in unit cell.
Background technology
Groove MOSFET device is widely used in the power class circuit, connects power supply and load as switching device.For a long time, how to reduce power loss is subject under discussion of greatest concern always, is especially advocating energy-saving and emission-reduction, today of low-carbon (LC).
Fig. 1 is for using the DC-to-DC conversion control circuit schematic diagram of metal-oxide-semiconductor as switching device.As can be seen from the figure, groove MOSFET device M1 (pipe down) and M2 (going up pipe) are exactly the core switching device as this circuit, realize the DC-to-DC conversion by control chip, wherein, itself there are parasitic diode D1, D2 (constituting) among M1 and the M2, and are effectively to reduce the HF switch loss between the source S of M1 and drain D, to have designed Schottky diode SBD (as shown in the figure) by the P type well region/drain electrode of surrounding source electrode.In this circuit working process, M1 and M2 can be in off state simultaneously under a certain state, for proof load obtains electric current supply continuously, parasitic diode D1 among the M1 opens, but because Schottky diode SBD compares with parasitic diode D1 (PN junction), has lower cut-in voltage (about Schottky diode 0.3V, about PN junction diode 0.7V), a Schottky diode SBD (as shown in Figure 2) in parallel between the source S of M1 and drain D can effectively reduce because the loss that causes falls in high cut-in voltage.In addition, Schottky diode has shorter reverse recovery time, more can effectively reduce the switching loss in the HF switch process.
In the past, in order to have experienced following three phases at a Schottky diode SBD in parallel between the source S of groove MOSFET device and the drain D:
Phase I is that the groove MOSFET with the Schottky diode of individual packages and individual packages is installed in parallel on circuit board.Shortcoming is the cost height, takies board area and because the influence of longer cabling introducing stray inductance.
Second stage is that Schottky chip independently is encapsulated in the same semiconductor packages with independently the groove MOSFET chip is in parallel.Shortcoming still is the cost height, and encapsulation back chip area is big.
Phase III is that groove MOSFET and Schottky diode are designed and produced in same chip, such as U.S. Pat 7446374, US6433396, US6987305 and US6351018 etc.These patents all are to adopt zoning design to add to distinguish the scheme of making on the mode of handling groove MOSFET and Schottky diode, promptly in each patent, can correspondence find groove MOSFET district and schottky diode area, and on semiconductor fabrication, be distinguished by extra light shield always for the difference in functionality of realizing groove MOSFET and Schottky diode.Therefore the shortcoming that exists always: 1, Schottky diode structure has taken a large amount of silicon face areas, causes chip area big, the cost height; 2, need the extra light shield that increases, carry out photoetching, complex process, cost height.For this reason, how overcoming above-mentioned deficiency is the problem that the present invention studies.
Summary of the invention
The invention provides a kind of in unit cell the groove MOS device and the manufacture method of integrated schottky diode, purpose is that rational and effective utilizes the semiconductor space, simplified structure, reduces cost, improves performance, overcomes above-mentioned the deficiencies in the prior art.
For achieving the above object, the technical scheme that groove MOS device of the present invention adopts is: the groove N type MOS device of integrated schottky diode in a kind of unit cell, on top plan view, the central authorities of this device are unit cell array region in parallel, the end face of unit cell array region deposits metal level, the bottom of unit cell array region is followed successively by lower metal layer from bottom to top, N+ monocrystalline substrate and N-epitaxial loayer, in the N-epitaxial loayer, vertical and horizontal are all parallel to offer some grooves, some the grooves that parallel longitudinal is offered are in the same horizontal plane and mutually with horizontal parallel some the grooves of offering and intersect, the inner surface of every groove is all grown gate oxide, and deposit the highly doped grid conductive polycrystalline silicon of N type in the groove, this grid conductive polycrystalline silicon is drawn gate metal electrode as metal-oxide-semiconductor by groove from the last metal level of unit cell array region periphery.
On top plan view, the groove that two adjacent parallel longitudinals are offered all surrounds a zone with two parallel grooves of offering of adjacent transverse, and this zone central vertical is to having contact hole, and contact hole extends in the N-epitaxial loayer from the lower surface of last metal level always.
Passing through on the lateral cross section of contact hole, the groove top of vertically offering is provided with dielectric layer, be provided with the medium side wall between this dielectric layer and the contact hole sidewall, below the medium side wall and between groove and contact hole, be provided with N+ source region and P type trap downwards successively, P type trap is provided with the P+ contact zone by contact hole one side; The contact hole inner surface deposits Titanium tack coat and titanium nitride barrier layer successively, Titanium tack coat and titanium nitride barrier layer form N+ source electrode ohmic contact at contact hole sidewall and N+ source region, ohmic contact at contact hole sidewall and P+ contact area formation P type trap forms Schottky contacts (Schottky barrier) in the contact hole bottom with the N-epitaxial loayer; Being filled with metal in the contact hole is connected with the last metal level of unit cell array region, the last metal level of unit cell array region forms metal-oxide-semiconductor source metal electrode, also be the anode metal electrode of Schottky diode simultaneously, described lower metal layer forms metal-oxide-semiconductor drain metal electrode, also is the cathodic metal electrode of Schottky diode simultaneously.
For achieving the above object, the technical scheme that groove MOS device manufacture method of the present invention adopts is: the groove MOS device manufacture method of integrated schottky diode in a kind of unit cell comprises following process steps:
The first step. on the N+ monocrystalline substrate of N type high-dopant concentration, the N-epitaxial loayer of growth N type low doping concentration.
Second step. at N-epitaxial loayer upper surface first dielectric layer of growing, this first dielectric layer is a silicon dioxide layer, perhaps silicon nitride layer, the perhaps composite bed of silicon dioxide layer and silicon nitride layer.
The 3rd step. first dielectric layer is implemented photoetching, the P type trap figure of definition metal-oxide-semiconductor unit cell array.
The 4th step. adopt dry etching method, selectivity is removed first dielectric layer of not protected by photoresist, exposes the N-epitaxial loayer of described P type trap figure correspondence, uses as the first hard mask and remove first dielectric layer that remains behind the photoresist.
The 5th step. the upper surface of the 4th step back total is implemented the p type impurity ion inject, the p type impurity ion is injected in the N-epitaxial loayer that does not have the first hard mask covering, in the N-epitaxial loayer, form P type well area by quick thermal annealing process then, the width dimensions decision that the distance between the adjacent P type trap is covered on this direction by the first hard mask.
The 6th step. at upper surface uniform deposition second dielectric layer of the 5th step back total, this second dielectric layer is a silicon dioxide layer, perhaps silicon nitride layer, the perhaps composite bed of silicon dioxide layer and silicon nitride layer.
The 7th step. second dielectric layer is implemented dry etching, dry etching is removed second thickness of dielectric layers that the thickness of second dielectric layer equals to deposit, because of dry etching is vertical etching, make second dielectric layer that is not etched away form the first medium side wall at the sidewall of the described first hard mask structure, the first hard mask and the first medium side wall form the second hard mask together, and the zone beyond the second hard mask exposes the N-epitaxial loayer.
The 8th the step. with the second hard mask as protection; adopt the dry etching method selective etch to expose the monocrystalline silicon in N-epitaxial loayer zone; in P type trap, form groove; gash depth is greater than the degree of depth of P type trap; trenched side-wall is surrounded by P type trap; the P type trap width of trenched side-wall is by the width decision of the first medium side wall correspondence.
The 9th step. adopt wet etching method, the selective removal second hard mask, the i.e. first hard mask and the first medium side wall.
The tenth step. at the even growthing silica layer of upper surface of the 9th step back total, as gate oxide.
The 11 step. at the highly doped conductive polycrystalline silicon floor of upper surface deposition N type of the tenth step back total, the highly doped conductive polycrystalline silicon of N type fills up the groove that the surface has silicon dioxide layer.
The 12 step. the highly doped conductive polycrystalline silicon floor of the N type of deposition is implemented dry etching, remove the highly doped conductive polycrystalline silicon of N type of total upper surface, the top of the highly doped conductive polycrystalline silicon of N type that is filled in groove is with till N-epitaxial loayer top flushes, thereby forms the grid conductive polycrystalline silicon.
The 13 step. the upper surface to the 12 step back total is implemented photoetching, and the figure of definition metal-oxide-semiconductor unit cell array region exposes the unit cell array region.
The 14 step. the unit cell array region is implemented N type foreign ion inject, form the N+ source region at N-epitaxial loayer top by heat treatment then.
The 15 step. at upper surface uniform deposition the 3rd dielectric layer of the 14 step back total, the 3rd dielectric layer is a silicon dioxide layer, perhaps silicon nitride layer, the perhaps composite bed of silicon dioxide layer and silicon nitride layer.
The 16 step. the 3rd dielectric layer is implemented photoetching, the P+ contact zone figure of definition metal-oxide-semiconductor unit cell array, this P+ contact zone is positioned at each unit cell central authorities, and be connected across between two adjacent P type traps, the width of P+ contact zone is greater than the interval between two adjacent P type traps, simultaneously less than the interval between two adjacent trenches.
The 17 step. adopt dry etching method, selectivity is removed the 3rd dielectric layer of not protected by photoresist, exposes the N-epitaxial loayer of described P+ contact zone correspondence, uses as the 3rd hard mask and remove the 3rd dielectric layer that remains behind the photoresist.
The 18 the step. with the 3rd hard mask as protection; the upper surface of the 17 step back total is implemented the p type impurity ion to be injected; and, below the N+ source region, forming the P+ contact zone by regulating the p type impurity ion implantation energy, this P+ contact zone and adjacent two P type well areas have overlapping.
The 19 step. at upper surface uniform deposition the 4th dielectric layer of the 18 step back total, the 4th dielectric layer is a silicon dioxide layer, perhaps silicon nitride layer, the perhaps composite bed of silicon dioxide layer and silicon nitride layer.
The 20 step. the 4th dielectric layer is implemented dry etching, dry etching is removed the 4th thickness of dielectric layers that the thickness of the 4th dielectric layer equals to deposit, because of dry etching is vertical etching, make the 4th dielectric layer that is not etched away form the second medium side wall at the sidewall of the described the 3rd hard mask structure, the 3rd hard mask and the second medium side wall form the 4th hard mask together, and the zone beyond the 4th hard mask exposes the N-epitaxial loayer.
The 21 the step. with the 4th hard mask as protection; the monocrystalline silicon that adopts the dry etching method selective etch to expose in the N-epitaxial loayer forms contact hole; the below of described P+ contact zone is stretched in the bottom of contact hole; and touching N-epitaxial loayer zone, the sidewall of contact hole has N+ source region and P+ contact zone.
The 22 step. plated metal titanium tack coat and titanium nitride barrier layer successively in contact hole, make Titanium tack coat and titanium nitride barrier layer form N+ source electrode ohmic contact by heat treatment then at contact hole sidewall and N+ source region, ohmic contact at contact hole sidewall and P+ contact area formation P type trap forms Schottky contacts (Schottky barrier) in the contact hole bottom with the N-epitaxial loayer.
The 23 step. metal level on the upper surface deposition of the 22 step back total.
The 24 step. last metal level is implemented photoetching; protect the source metal electrode zone of metal-oxide-semiconductor unit cell array area and the gate metal electrode zone of metal-oxide-semiconductor unit cell array area periphery with photoresist, promptly define source metal electrode zone and gate metal electrode zone figure.
The 25 step. adopt dry etching method; the last metal level that selective removal is not protected by photoresist; expose the 3rd dielectric layer; after removing photoresist; the last metal level that is positioned at the unit cell array region that stays forms metal-oxide-semiconductor source metal electrode; also be the anode metal electrode of Schottky diode simultaneously, the last metal level that is positioned at unit cell array region periphery that stays forms metal-oxide-semiconductor gate metal electrode.
The 26 step. at the bottom surface of N+ monocrystalline substrate deposition lower metal layer, this lower metal layer forms metal-oxide-semiconductor drain metal electrode, also is the cathodic metal electrode of Schottky diode simultaneously.
The principle of the invention and effect are: the silicon chip of N type groove MOFET device is made of the N-epitaxial loayer of growth N type low doping concentration on the N+ monocrystalline substrate of N type high-dopant concentration.The MOSFET drain electrode is positioned at the highly doped part in silicon chip bottom surface, and source electrode is positioned at the more low-doped epitaxial loayer part of silicon chip surface, and grid then is made of the groove perpendicular to silicon chip surface.The maximum reverse bias voltage that the groove MOSFET chip can bear is by the thickness and the doping content decision of epitaxial loayer, and then by the width of conducting channel, promptly total length of side of groove determines the size of conducting electric current.Under limited area, the groove periodic arrangement is in the hope of obtaining maximum effective length of side.The minimum repetitive that includes groove, source electrode is called unit cell, and each unit cell is a complete MOSFET device.These unit cells are connected in parallel, and constitute the MOSFET chip.The characteristics of the technology of the present invention innovation are:
1. Schottky diode structure is integrated in each groove MOSFET unit cell.Groove MOSFET with this structure can effectively reduce switching loss in power application.
2.N+ the ohmic contact of the ohmic contact of source electrode, P type trap and Schottky diode anode contact shared same contact hole, effectively the save silicon surface area reduces chip cost.
3. integrated schottky diode structure in the groove MOSFET unit cell does not need extra light shield and lithography step on manufacturing process.But introduce the medium side wall (constituting the side wall material can be silicon dioxide, perhaps silicon nitride, perhaps both have both at the same time) and the self-registered technology of easier control.In manufacture process, medium side wall and self-registered technology are used in following two committed steps:
For the first time be after P type trap ion injects, before the etching groove.Specifically: after the first hard mask pattern definition finishes, carry out P type trap ion and inject, utilize stopping of the first hard mask, between two adjacent P type traps, form enough spaces, the N-epitaxial loayer is touched be used for the contact hole of source electrode and the contact of P type trap, form Schottky contacts.Form the first medium side wall by deposition and etching second dielectric layer in the side of the first hard mask structure then, carry out etching groove again, can perfectly realize of the uniform encirclement of P type trap groove.
For the second time be after being used to realize the P+ contact zone ion injection of P type trap ohmic contact, before the contact hole silicon etching.Specifically: form the 3rd hard mask after to the 3rd dielectric layer etching, the ion that carries out the P+ contact zone injects.Form the second medium side wall by deposition and etching the 4th dielectric layer at the sidewall of the 3rd hard mask structure subsequently.The second medium side wall after the silicon contact hole etching in, can effectively keep the P+ contact area.Keep enough P+ contact areas two significances are arranged: the one, be used to form the ohmic contact of P type trap; The 2nd, can effectively suppress by of the action of source electrode/P type trap/N-epitaxial loayer with the parasitic bipolar transistor that forms of drain electrode, this parasitic bipolar transistor is in case open, groove MOSFET device will not controlled by grid, between drain electrode and source electrode, big current lead-through is arranged, produce a large amount of heats, groove MOSFET device burns the most at last.
In a word, by the application of medium side wall and self-registered technology, can obtain simultaneously that low cost, processing step are simple, the groove MOSFET device of high-performance and highly reliable type.
Description of drawings
Accompanying drawing 1 is the DC-to-DC conversion control circuit schematic diagram of metal-oxide-semiconductor as switching device;
Accompanying drawing 2 is the groove MOSFET device circuit diagram of Schottky diode in parallel;
Accompanying drawing 3 is for being integrated with the groove MOSFET device schematic top plan view of Schottky diode in the embodiment of the invention 1 unit cell;
Accompanying drawing 4 is the A-A profile of Fig. 3;
Accompanying drawing 5A～5F is the embodiment of the invention 1 a groove MOSFET device manufacture craft schematic flow sheet;
Accompanying drawing 6 is the embodiment of the invention 2 groove MOSFET device profiles;
Accompanying drawing 7A～7B inventive embodiments 2 groove MOSFET device manufacture craft schematic diagrames;
Accompanying drawing 8 is the embodiment of the invention 3 groove MOSFET device profiles;
Accompanying drawing 9A～9B inventive embodiments 3 groove MOSFET device manufacture craft schematic diagrames;
Accompanying drawing 10 is the embodiment of the invention 4 groove MOSFET device profiles.
In the above accompanying drawing: 1, unit cell array region; 2, guard ring; 3, by ring; 4, groove; 5, contact hole; 6, unit cell; 7, gate electrode wire lead termination; 8, the second medium side wall; 9, go up metal level; 10, N+ monocrystalline substrate; 11, N-epitaxial loayer; 12, gate oxide; 13, grid conductive polycrystalline silicon; 14, the 3rd dielectric layer; 15, N+ source region; 16, P type trap; 17, P+ contact zone; 18, Titanium tack coat; 19, titanium nitride barrier layer; 20, first dielectric layer; 21, the first medium side wall; 22, gate oxide; 23, auxiliary silicon dioxide layer; 24, photoresist; 25, polysilicon barrier bed; 26, auxiliary silicon dioxide layer; 27, p type island region territory.
Embodiment
Below in conjunction with drawings and Examples the present invention is further described:
Embodiment 1:
As shown in Figure 3 and Figure 4, the groove N type MOS device architecture of integrated schottky diode is in the unit cell of the present invention: on top plan view, central authorities are unit cell array region 1 in parallel, and unit cell array region 1 periphery is provided with guard ring 2 and by terminal protection structures such as rings 3.The end face of unit cell array region 1 deposits metal level 9, and metal level 9 is a metallic aluminium on this, perhaps is doped with the metallic aluminium of copper, perhaps is doped with the metallic aluminium of copper and silicon.The bottom of unit cell array region 1 is followed successively by lower metal layer (not drawing among the figure), N+ monocrystalline substrate 10 and N-epitaxial loayer 11 from bottom to top.In the N-epitaxial loayer 11, all parallel some the grooves 4 that offer of vertical and horizontal, some the grooves 4 that parallel longitudinal is offered are in the same horizontal plane and mutually with horizontal parallel some the grooves of offering 4 and intersect, the inner surface of every groove 4 is all grown gate oxide 12, and deposit the highly doped grid conductive polycrystalline silicon 13 of N type in the groove 4, this grid conductive polycrystalline silicon 13 is drawn gate metal electrode as metal-oxide-semiconductor from the gate electrode wire lead termination 7 of unit cell array region 1 periphery by last metal level 9 by groove 4.
(see figure 3) on top plan view, the groove 4 that two adjacent parallel longitudinals are offered all surrounds a zone with two parallel grooves of offering 4 of adjacent transverse, this zone central vertical is to having contact hole 5, and contact hole 5 extends in the N-epitaxial loayer 11 from the lower surface of last metal level 9 always.
Passing through (see figure 4) on the lateral cross section of contact hole 5, groove 4 tops of vertically offering are provided with between the 3rd dielectric layer 14, the three dielectric layers 14 and contact hole 5 sidewalls and are provided with the second medium side wall 8.Below the second medium side wall 8 and between groove 4 and contact hole 5, be provided with N+ source region 15 and P type trap 16 downwards successively, P type trap 16 is provided with P+ contact zone 17 by contact hole 5 one sides.Contact hole 5 inner surfaces deposit Titanium tack coat 18 and titanium nitride barrier layer 19 successively, Titanium tack coat 18 and titanium nitride barrier layer 19 form N+ source electrode ohmic contact at contact hole 5 sidewalls and N+ source region 15, ohmic contact at contact hole 5 sidewalls and P+ contact area 17 formation P type traps forms Schottky contacts (Schottky barrier) in contact hole 5 bottoms and N-epitaxial loayer 11.Be filled with tungsten in the contact hole 5 (when the contact hole diameter is enough big, can fill metallic aluminium, perhaps be doped with the metallic aluminium of copper, perhaps be doped with the metallic aluminium of copper and silicon) be connected with the last metal level 9 of unit cell array region 1, the last metal level 9 of unit cell array region 1 forms metal-oxide-semiconductor source metal electrode, also is the anode metal electrode of Schottky diode simultaneously.And lower metal layer forms metal-oxide-semiconductor drain metal electrode, also is the cathodic metal electrode of Schottky diode simultaneously.
Based on above-mentioned groove N type MOS device architecture, manufacture method of the present invention comprises following process steps:
Referring to Fig. 5 A:
The first step. on the N+ monocrystalline substrate 10 of N type high-dopant concentration, the N-epitaxial loayer 11 of growth N type low doping concentration.
Second step. at N-epitaxial loayer 11 upper surfaces first dielectric layer 20 of growing, this first dielectric layer 20 is a silicon dioxide layer, perhaps silicon nitride layer, the perhaps composite bed of silicon dioxide layer and silicon nitride layer.Present embodiment selects silicon dioxide layer as first dielectric layer 20.
The 3rd step. first dielectric layer 20 is implemented photoetching, the P type trap figure of definition metal-oxide-semiconductor unit cell array.The figure (see figure 3) of this P type trap figure similar groove 4 definition on top plan view, but P type trap width is greater than groove 4.
The 4th step. adopt dry etching method, selectivity is removed first dielectric layer of not protected by photoresist 20, exposes the N-epitaxial loayer 11 of described P type trap figure correspondence, uses as the first hard mask and remove first dielectric layer 20 that remains behind the photoresist.
The 5th step. the upper surface of the 4th step back total is implemented the p type impurity ion inject, the p type impurity ion is injected in the N-epitaxial loayer 11 that does not have the first hard mask covering, in N-epitaxial loayer 11, form P type trap 16 zones by quick thermal annealing process then, the width dimensions decision that the distance between the adjacent P type trap 16 is covered on this direction by the first hard mask.
Referring to Fig. 5 B:
The 6th step. at upper surface uniform deposition second dielectric layer of the 5th step back total, this second dielectric layer is a silicon dioxide layer, perhaps silicon nitride layer, the perhaps composite bed of silicon dioxide layer and silicon nitride layer.
The 7th step. second dielectric layer is implemented dry etching, dry etching is removed second thickness of dielectric layers that the thickness of second dielectric layer equals to deposit, because of dry etching is vertical etching, make second dielectric layer that is not etched away form the first medium side wall 21 at the sidewall of the described first hard mask structure, the first hard mask and the first medium side wall 21 form the second hard mask together, and the zone beyond the second hard mask exposes N-epitaxial loayer 11.
The 8th the step. with the second hard mask as protection; adopt the dry etching method selective etch to expose the monocrystalline silicon in N-epitaxial loayer 11 zones; in P type trap 16, form groove 4; groove 4 degree of depth are greater than the degree of depth of P type trap 16; groove 4 sidewalls are surrounded by P type trap 16; P type trap 16 width of groove 4 sidewalls are by the width decision of the first medium side wall, 21 correspondences.
Referring to Fig. 5 C:
The 9th step. adopt wet etching method, the selective removal second hard mask, the i.e. first hard mask and the first medium side wall 21.
The tenth step. at the even growthing silica layer of upper surface of the 9th step back total, as gate oxide 12.
The 11 step. at the highly doped conductive polycrystalline silicon floor of upper surface deposition N type of the tenth step back total, the highly doped conductive polycrystalline silicon of N type fills up the groove 4 that the surface has silicon dioxide layer.
The 12 step. the highly doped conductive polycrystalline silicon floor of the N type of deposition is implemented dry etching, remove the highly doped conductive polycrystalline silicon of N type of total upper surface, the top of the highly doped conductive polycrystalline silicon of N type that is filled in groove 4 is with till N-epitaxial loayer 11 tops flush, thereby forms grid conductive polycrystalline silicon 13.
The 13 step. the upper surface to the 12 step back total is implemented photoetching, and the figure of definition metal-oxide-semiconductor unit cell array region 1 exposes unit cell array region 1.
The 14 step. unit cell array region 1 is implemented N type foreign ion inject, form N+ source region 15 at N-epitaxial loayer 11 tops by heat treatment then.
Referring to Fig. 5 D:
The 15 step. upper surface uniform deposition the 3rd dielectric layer 14, the three dielectric layers 14 in the 14 step back total are silicon dioxide layer, perhaps silicon nitride layer, the perhaps composite bed of silicon dioxide layer and silicon nitride layer.
The 16 step. the 3rd dielectric layer 14 is implemented photoetching, the P+ contact zone figure of definition metal-oxide-semiconductor unit cell array, this P+ contact zone 17 is positioned at each unit cell central authorities, and be connected across between two adjacent P type traps 16, the width of P+ contact zone 17 is greater than the interval between two adjacent P type traps 16, simultaneously less than the interval between two adjacent trenches 4.
The 17 step. adopt dry etching method, selectivity is removed the 3rd dielectric layer of not protected by photoresist 14, exposes the N-epitaxial loayer 11 of described P+ contact zone 17 correspondences, uses as the 3rd hard mask and remove the 3rd dielectric layer 14 that remains behind the photoresist.
The 18 the step. with the 3rd hard mask as protection; the upper surface of the 17 step back total is implemented the p type impurity ion to be injected; and by regulating the p type impurity ion implantation energy; form P+ contact zone 17 below N+ source region 15, there is overlapping this P+ contact zone 17 with adjacent two P type trap 16 zones.
Referring to Fig. 5 E:
The 19 step. at upper surface uniform deposition the 4th dielectric layer of the 18 step back total, the 4th dielectric layer is a silicon dioxide layer, perhaps silicon nitride layer, the perhaps composite bed of silicon dioxide layer and silicon nitride layer.
The 20 step. the 4th dielectric layer is implemented dry etching, dry etching is removed the 4th thickness of dielectric layers that the thickness of the 4th dielectric layer equals to deposit, because of dry etching is vertical etching, make the 4th dielectric layer that is not etched away form the second medium side wall 8 at the sidewall of the described the 3rd hard mask structure, the 3rd hard mask and the second medium side wall 8 form the 4th hard mask together, and the zone beyond the 4th hard mask exposes N-epitaxial loayer 11.This moment, the below of the second medium side wall 8 was followed successively by N+ source region 15, P+ contact zone 17 and P type trap 16 zones in N-epitaxial loayer 11.
The 21 the step. with the 4th hard mask as protection; the monocrystalline silicon that adopts the dry etching method selective etch to expose in the N-epitaxial loayer 11 forms contact hole 5; the below of described P+ contact zone 17 is stretched in the bottom of contact hole 5; and touching N-epitaxial loayer 11 zones, the sidewall of contact hole 5 has N+ source region 15 and P+ contact zone 17.
Referring to Fig. 5 F:
The 22 step. plated metal titanium tack coat 18 and titanium nitride barrier layer 19 successively in contact hole 5, make Titanium tack coat 18 and titanium nitride barrier layer 19 form N+ source electrode ohmic contact by heat treatment then at contact hole 5 sidewalls and N+ source region 15, ohmic contact at contact hole 5 sidewalls and P+ contact zone 17 formation P type traps forms Schottky contacts (Schottky barrier) in contact hole 5 bottoms and N-epitaxial loayer 11.
The 23 step. metal level 9 on the upper surface deposition of the 22 step back total.If contact hole 5 diameters are less, elder generation is at the upper surface plated metal tungsten of total, tungsten fills up contact hole 5, adopt dry etching method then, selectivity is removed tungsten, and the 3rd dielectric layer top exposed is come out, and still fill up tungsten in the contact hole 5, then, perhaps be doped with the aluminium lamination of copper, perhaps be doped with the aluminium lamination of copper and silicon at total upper surface deposition aluminium lamination.If contact hole 5 diameters are enough big, can perhaps be doped with the aluminium lamination of copper directly at the upper surface deposition aluminium lamination of total, perhaps be doped with the aluminium lamination of copper and silicon, and fill up contact hole 5.
The 24 step. last metal level 9 is implemented photoetching; protect the source metal electrode zone of metal-oxide-semiconductor unit cell array area and the gate metal electrode zone of metal-oxide-semiconductor unit cell array area periphery with photoresist, promptly define source metal electrode zone and gate metal electrode zone figure.
The 25 step. adopt dry etching method; selective removal (is not comprised aluminium lamination by the last metal level 9 that photoresist is protected; titanium nitride layer; titanium layer); expose the 3rd dielectric layer, behind the removal photoresist, the last metal level that is positioned at unit cell array region 19 that stays forms metal-oxide-semiconductor source metal electrodes; also be the anode metal electrode of Schottky diode simultaneously, the last metal level that is positioned at unit cell array region 1 periphery 9 that stays forms metal-oxide-semiconductor gate metal electrode.
The 26 step. at the bottom surface of N+ monocrystalline substrate 10 deposition lower metal layer (not drawing among the figure), this lower metal layer forms metal-oxide-semiconductor drain metal electrode, also is the cathodic metal electrode of Schottky diode simultaneously.
Embodiment 2:
As shown in Figure 6, present embodiment is compared difference with embodiment 1 and is: gate oxide 22 thickenings of groove 4 bottoms, be gate oxide 12 thickness of gate oxide 22 thickness of groove 4 bottoms greater than groove 4 sidewalls, other structures are basic identical, no longer are repeated in this description here.22 thickenings of groove 4 bottom gate oxide layers can bring 2 benefits: the one, and the parasitic capacitance between grid and the drain electrode diminishes.Can reduce the switch power loss in the MOSFET device dynamic open and close process.The 2nd, when the MOSFET raceway groove turn-offs, because there is very big bias voltage in drain electrode, can have highfield in the channel bottom zone, thicker gate oxide 22 can improve the ability that device is resisted highfield, avoids taking place puncturing the component failure that causes because of drain-to-gate.
The manufacture method that adopts for gate oxide 22 thickenings that make groove 4 bottoms is: based on the processing step of embodiment 1, add following steps between the 9th step and the tenth step:
Referring to Fig. 7 A:
The auxiliary silicon dioxide layer 23 (seeing Fig. 7 A, compare that the thickness of the auxiliary silicon dioxide layer 23 of this step is bigger) that is used to increase groove 4 bottom gate oxide layers 22 thickness in the even growth of upper surface of the 9th step back total with gate oxide 12; Implement photoetching at the upper surface coating photoresist of total then; Then adopt dry etching method selective etch photoresist, retain photoresist 24 (seeing Fig. 7 A) in groove 4 bottoms.
Referring to Fig. 7 B:
Then adopt wet etching method to remove the auxiliary silicon dioxide layer 23 on surface,, make groove 4 bottoms still remain with auxiliary silicon dioxide layer 23 because stopping of photoresist 24 retained in groove 4 bottoms; Remove photoresist at last and form the auxiliary silicon dioxide layer that groove 4 bottoms are used to thicken.
Embodiment 3:
As shown in Figure 8, present embodiment is compared difference with embodiment 1 and is: groove 4 bottoms have increased polysilicon barrier bed 25, and this polysilicon barrier bed 25 is arranged in the below of groove 4 grid conductive polycrystalline silicons 13.Other structures are basic identical, no longer are repeated in this description here.The benefit that increases polysilicon barrier bed 25 in groove 4 bottoms is mainly the parasitic capacitance that reduces between grid and the drain electrode.This structure can reduce the switch power loss in the MOSFET device dynamic open and close process.
The manufacture method that groove 4 bottoms increase by 25 employings of polysilicon barrier bed is: based on the processing step of embodiment 1, add following steps between the 9th step and the tenth step:,
With reference to figure 9A:
The auxiliary silicon dioxide layer 26 (compare with gate oxide 12, the thickness of the auxiliary silicon dioxide layer 26 of this step is bigger) that is used to make groove 4 bottom polysilicon barrier beds 25 in the even growth of upper surface of the 9th step back total; Upper surface in total deposits the polysilicon layer that is used to block then, and this polysilicon fills up groove 4; Then adopt dry etching method selective etch conductive polycrystalline silicon, only keep conductive polycrystalline silicon floor at channel bottom.
With reference to figure 9B:
Then adopt wet etching method to remove the auxiliary silicon dioxide layer 26 on total surface, owing to keep stopping of polysilicon layer, groove 4 bottoms still remain with auxiliary silicon dioxide layer 26, and keep the polysilicon barrier bed 25 that conductive polycrystalline silicon floor increases as groove 4 bottoms.
Embodiment 4:
As shown in figure 10, present embodiment is compared difference with embodiment 1 and is: be provided with p type island region territory 27 in the N-epitaxial loayer 11 at place, contact hole 5 base angles, the base angle that this p type island region territory 27 surrounds contact hole 5 can reduce the reverse leakage current of Schottky diode, and contact hole 5 bottoms are according to contacting with N-epitaxial loayer 11.
Manufacture method is: based on the processing step of embodiment 1, add following steps between the 21 step and the 22 step:
Implement the p type impurity ion and inject, adjust the implant angle (see figure 10), utilize stopping of contact hole 5 sidewalls, form p type island region territory 27 in the N-epitaxial loayer 11 that contact hole 5 base angles are located.
The foregoing description only is explanation technical conceive of the present invention and characteristics, and its purpose is to allow the personage who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.All equivalences that spirit is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.
Claims (10)
1. the groove N type MOS device of integrated schottky diode in the unit cell, on top plan view, the central authorities of this device are unit cell array region in parallel, the end face of unit cell array region deposits metal level, the bottom of unit cell array region is followed successively by lower metal layer from bottom to top, N+ monocrystalline substrate and N-epitaxial loayer, in the N-epitaxial loayer, vertical and horizontal are all parallel to offer some grooves, some the grooves that parallel longitudinal is offered are in the same horizontal plane and mutually with horizontal parallel some the grooves of offering and intersect, the inner surface of every groove is all grown gate oxide, and deposit the highly doped grid conductive polycrystalline silicon of N type in the groove, this grid conductive polycrystalline silicon is drawn gate metal electrode as metal-oxide-semiconductor by groove from the last metal level of unit cell array region periphery, it is characterized in that:
On top plan view, the groove that two adjacent parallel longitudinals are offered all surrounds a zone with two parallel grooves of offering of adjacent transverse, and this zone central vertical is to having contact hole, and contact hole extends in the N-epitaxial loayer from the lower surface of last metal level always;
Passing through on the lateral cross section of contact hole, the groove top of vertically offering is provided with dielectric layer, be provided with the medium side wall between this dielectric layer and the contact hole sidewall, below the medium side wall and between groove and contact hole, be provided with N+ source region and P type trap downwards successively, P type trap is provided with the P+ contact zone by contact hole one side; The contact hole inner surface deposits Titanium tack coat and titanium nitride barrier layer successively, Titanium tack coat and titanium nitride barrier layer form N+ source electrode ohmic contact at contact hole sidewall and N+ source region, ohmic contact at contact hole sidewall and P+ contact area formation P type trap forms Schottky contacts in the contact hole bottom with the N-epitaxial loayer; Being filled with metal in the contact hole is connected with the last metal level of unit cell array region, the last metal level of unit cell array region forms metal-oxide-semiconductor source metal electrode, also be the anode metal electrode of Schottky diode simultaneously, described lower metal layer forms metal-oxide-semiconductor drain metal electrode, also is the cathodic metal electrode of Schottky diode simultaneously.
2. groove N type MOS device according to claim 1, it is characterized in that: the gate oxide thickness of described channel bottom is greater than the gate oxide thickness of trenched side-wall.
3. groove N type MOS device according to claim 1, it is characterized in that: described channel bottom is provided with the conductive polycrystalline silicon barrier bed, and this conductive polycrystalline silicon barrier bed is arranged in the below of groove grid conductive polycrystalline silicon.
4. groove N type MOS device according to claim 1 is characterized in that: be provided with the p type island region territory in the N-epitaxial loayer at place, described contact hole base angle, this p type island region territory surrounds the base angle of contact hole, and the contact hole bottom is according to contacting with the N-epitaxial loayer.
5. manufacture method according to the described groove N of claim 1 type MOS device is characterized in that comprising following process steps:
The first step. on the N+ monocrystalline substrate of N type high-dopant concentration, the N-epitaxial loayer of growth N type low doping concentration;
Second step. at N-epitaxial loayer upper surface first dielectric layer of growing, this first dielectric layer is a silicon dioxide layer, perhaps silicon nitride layer, the perhaps composite bed of silicon dioxide layer and silicon nitride layer;
The 3rd step. first dielectric layer is implemented photoetching, the P type trap figure of definition metal-oxide-semiconductor unit cell array;
The 4th step. adopt dry etching method, selectivity is removed first dielectric layer of not protected by photoresist, exposes the N-epitaxial loayer of described P type trap figure correspondence, uses as the first hard mask and remove first dielectric layer that remains behind the photoresist;
The 5th step. the upper surface of the 4th step back total is implemented the p type impurity ion inject, the p type impurity ion is injected in the N-epitaxial loayer that does not have the first hard mask covering, in the N-epitaxial loayer, form P type well area by quick thermal annealing process then, the width dimensions decision that the distance between the adjacent P type trap is covered on this direction by the first hard mask;
The 6th step. at upper surface uniform deposition second dielectric layer of the 5th step back total, this second dielectric layer is a silicon dioxide layer, perhaps silicon nitride layer, the perhaps composite bed of silicon dioxide layer and silicon nitride layer;
The 7th step. second dielectric layer is implemented dry etching, dry etching is removed second thickness of dielectric layers that the thickness of second dielectric layer equals to deposit, because of dry etching is vertical etching, make second dielectric layer that is not etched away form the first medium side wall at the sidewall of the described first hard mask structure, the first hard mask and the first medium side wall form the second hard mask together, and the zone beyond the second hard mask exposes the N-epitaxial loayer;
The 8th the step. with the second hard mask as protection, adopt the dry etching method selective etch to expose the monocrystalline silicon in N-epitaxial loayer zone, in P type trap, form groove, gash depth is greater than the degree of depth of P type trap, trenched side-wall is surrounded by P type trap, the P type trap width of trenched side-wall is by the width decision of the first medium side wall correspondence;
The 9th step. adopt wet etching method, the selective removal second hard mask, the i.e. first hard mask and the first medium side wall;
The tenth step. at the even growthing silica layer of upper surface of the 9th step back total, as gate oxide;
The 11 step. at the highly doped conductive polycrystalline silicon floor of upper surface deposition N type of the tenth step back total, the highly doped conductive polycrystalline silicon of N type fills up the groove that the surface has silicon dioxide layer;
The 12 step. the highly doped conductive polycrystalline silicon floor of the N type of deposition is implemented dry etching, remove the highly doped conductive polycrystalline silicon of N type of total upper surface, the top of the highly doped conductive polycrystalline silicon of N type that is filled in groove is with till N-epitaxial loayer top flushes, thereby forms the grid conductive polycrystalline silicon;
The 13 step. the upper surface to the 12 step back total is implemented photoetching, and the figure of definition metal-oxide-semiconductor unit cell array region exposes the unit cell array region;
The 14 step. the unit cell array region is implemented N type foreign ion inject, form the N+ source region at N-epitaxial loayer top by heat treatment then;
The 15 step. at upper surface uniform deposition the 3rd dielectric layer of the 14 step back total, the 3rd dielectric layer is a silicon dioxide layer, perhaps silicon nitride layer, the perhaps composite bed of silicon dioxide layer and silicon nitride layer;
The 16 step. the 3rd dielectric layer is implemented photoetching, the P+ contact zone figure of definition metal-oxide-semiconductor unit cell array, this P+ contact zone is positioned at each unit cell central authorities, and be connected across between two adjacent P type traps, the width of P+ contact zone is greater than the interval between two adjacent P type traps, simultaneously less than the interval between two adjacent trenches;
The 17 step. adopt dry etching method, selectivity is removed the 3rd dielectric layer of not protected by photoresist, exposes the N-epitaxial loayer of described P+ contact zone correspondence, uses as the 3rd hard mask and remove the 3rd dielectric layer that remains behind the photoresist;
The 18 the step. with the 3rd hard mask as protection, the upper surface of the 17 step back total is implemented the p type impurity ion to be injected, and, below the N+ source region, forming the P+ contact zone by regulating the p type impurity ion implantation energy, this P+ contact zone and adjacent two P type well areas have overlapping;
The 19 step. at upper surface uniform deposition the 4th dielectric layer of the 18 step back total, the 4th dielectric layer is a silicon dioxide layer, perhaps silicon nitride layer, the perhaps composite bed of silicon dioxide layer and silicon nitride layer;
The 20 step. the 4th dielectric layer is implemented dry etching, dry etching is removed the 4th thickness of dielectric layers that the thickness of the 4th dielectric layer equals to deposit, because of dry etching is vertical etching, make the 4th dielectric layer that is not etched away form the second medium side wall at the sidewall of the described the 3rd hard mask structure, the 3rd hard mask and the second medium side wall form the 4th hard mask together, and the zone beyond the 4th hard mask exposes the N-epitaxial loayer;
The 21 the step. with the 4th hard mask as protection, the monocrystalline silicon that adopts the dry etching method selective etch to expose in the N-epitaxial loayer forms contact hole, the below of described P+ contact zone is stretched in the bottom of contact hole, and touching N-epitaxial loayer zone, the sidewall of contact hole has N+ source region and P+ contact zone;
The 22 step. plated metal titanium tack coat and titanium nitride barrier layer successively in contact hole, make Titanium tack coat and titanium nitride barrier layer form N+ source electrode ohmic contact by heat treatment then at contact hole sidewall and N+ source region, ohmic contact at contact hole sidewall and P+ contact area formation P type trap forms Schottky contacts in the contact hole bottom with the N-epitaxial loayer;
The 23 step. metal level on the upper surface deposition of the 22 step back total;
The 24 step. last metal level is implemented photoetching, protect the source metal electrode zone of metal-oxide-semiconductor unit cell array area and the gate metal electrode zone of metal-oxide-semiconductor unit cell array area periphery with photoresist, promptly define source metal electrode zone and gate metal electrode zone figure;
The 25 step. adopt dry etching method, the last metal level that selective removal is not protected by photoresist, expose the 3rd dielectric layer, after removing photoresist, the last metal level that is positioned at the unit cell array region that stays forms metal-oxide-semiconductor source metal electrode, also be the anode metal electrode of Schottky diode simultaneously, the last metal level that is positioned at unit cell array region periphery that stays forms metal-oxide-semiconductor gate metal electrode;
The 26 step. at the bottom surface of N+ monocrystalline substrate deposition lower metal layer, this lower metal layer forms metal-oxide-semiconductor drain metal electrode, also is the cathodic metal electrode of Schottky diode simultaneously.
6. manufacture method according to claim 5, it is characterized in that: in the 23 step, described upper surface deposition goes up metal level and is: at the upper surface plated metal tungsten of total, tungsten fills up contact hole, adopts dry etching method then earlier, selectivity is removed tungsten, the 3rd dielectric layer top exposed is come out, and still fill up tungsten in the contact hole, then at total upper surface deposition aluminium lamination, perhaps be doped with the aluminium lamination of copper, perhaps be doped with the aluminium lamination of copper and silicon.
7. manufacture method according to claim 5, it is characterized in that: in the 23 step, described upper surface deposition goes up metal level and is: at the upper surface deposition aluminium lamination of total, perhaps be doped with the aluminium lamination of copper, perhaps be doped with the aluminium lamination of copper and silicon, and fill up contact hole.
8. manufacture method according to claim 5 is characterized in that: add following steps between the 9th step and the tenth step:
The auxiliary silicon dioxide layer that is used to increase the channel bottom gate oxide thickness in the even growth of the upper surface of total; Implement photoetching at the upper surface coating photoresist of total then; Then adopt dry etching method selective etch photoresist, retain photoresist at channel bottom; Then adopt wet etching method to remove the auxiliary silicon dioxide layer on surface,, make channel bottom still remain with auxiliary silicon dioxide layer because channel bottom is retained stopping of photoresist; Remove photoresist at last and form the auxiliary silicon dioxide layer that channel bottom is used to thicken.
9. manufacture method according to claim 5 is characterized in that: add following steps between the 9th step and the tenth step:
The auxiliary silicon dioxide layer that is used to make channel bottom conductive polycrystalline silicon barrier bed in the even growth of the upper surface of total; Upper surface in total deposits the conductive polycrystalline silicon floor that is used to block then, and this conductive polycrystalline silicon fills up groove; Then adopt dry etching method selective etch conductive polycrystalline silicon, only keep conductive polycrystalline silicon floor at channel bottom; Then adopt wet etching method to remove the auxiliary silicon dioxide layer on total surface, owing to keep stopping of conductive polycrystalline silicon floor, channel bottom still remains with auxiliary silicon dioxide layer, and keeps the conductive polycrystalline silicon barrier bed that conductive polycrystalline silicon floor increases as channel bottom.
10. manufacture method according to claim 5 is characterized in that: add following steps between the 21 step and the 22 step:
Implement the p type impurity ion and inject, adjust implant angle, utilize stopping of contact hole sidewall, form the p type island region territory in the N-epitaxial loayer that the contact hole base angle is located, this p type island region territory surrounds the base angle of contact hole, and the contact hole bottom still keeps N-epitaxial loayer zone.
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