CN1017670B - Integrated circuit isolation process - Google Patents

Abstract

A multi-groove isolation process that avoids stress-induced defects by providing an almost smooth surface. The silicon substrate 10 is patterned and etched, resulting in active moat regions 18 and recesses (20a-b and 21a-b). A field oxide 40 is grown in the wide groove region 21 using the LOCOS method to fill the groove with oxide and a planarized field oxide 44 is deposited in the narrow groove region 20 . After the structure has been etched to obtain a flat surface, standard procedures are used to fabricate the active devices. This method uses only one photolithographic masking step, resulting in minimal loss of active area width.

Description

Generally speaking, the present invention belongs to the field of integrated circuits, and more specifically, the present invention relates to an isolation process applied to ultra-large scale integrated circuits with submicron dimensions.

In integrated circuit technology, it is necessary to separate the active regions (or "moat regions") of active devices from each other. In large-scale integrated circuits and ultra-large-scale integrated circuits using MOS technology, the method of LOCOS (local oxidation of silicon) is usually used to complete the isolation of the active area. To implement the LOCOS method, a patterned nitride on the surface of a thin oxide block is used to cover the area of the silicon substrate that will serve as the moat area. By exposing the uncovered area of the silicon substrate to a high temperature oxidizing environment, a relatively thick field oxide can be formed only in the exposed area.

However, the LOCOS process not only forms a field oxide in the vertical direction of the exposed silicon regions, but the oxide also grows laterally under the edge of the nitride mask. This lateral oxide etch beneath the nitride is called the "bird's beak" and can grow to about half the thickness of the oxide; thus, active area is wasted in this isolation process. As far as the standard LOCOS method is concerned, in order to reduce the "bird's beak", the thickness of the field oxide must be reduced appropriately, otherwise, the remaining "moat area" is not enough for the production of active devices. However, a reduction in field oxide thickness will degrade circuit performance due to increased interconnect capacitance. In addition, for a given voltage applied across a conductor through the field oxide, as the oxide thickness decreases, the leakage current between the "moats" under the field oxide increases rapidly, resulting in The isolation between adjacent areas becomes poor.

Several isolation processes have been developed to reduce the amount of oxide etch in the standard LOCOS process. In a method called SWAMI (Sidewall Masking Isolation), a A silicon etchant and sidewall nitride layers (silicon nitride layers formed on the sides of the recessed silicon regions) are used to suppress lateral erosion of the field oxide. The key to this near-zero erosion is the introduction of nitride sidewalls that are lifted up during oxide growth. Although the SWAMI process method reduces field oxide erosion, it has its limitations. One limitation is that the oxide mask (applied after the nitride sidewall layer) has a tendency to break at the junction of the first nitride and nitride sidewall layers. The occurrence of this fracture is mainly due to the normal over-etching in the vertical direction in the sidewall process. This fracture is confirmed by the localized erosion of the field oxide, especially at the corners of the pattern. easy to happen. Another limitation of this conventional SWAMI process approach is the increased sensitivity of the approach to defect generation in the silicon substrate due to the presence of nitride sidewalls. There is also a limitation that since a region adjacent to the moat region has a relatively thin nitride that does not contain enough channel stop impurities, double threshold will occur in the transistor characteristics Phenomenon.

There is an improvement to SWAMI, called the modified fully-framed-fully-recessed (MF ³ R) isolation method, which reduces the limitations of SWAMI. When the nitride, oxide, and recessed silicon layers are patterned and etched. Later, this process method uses an "undercut and backfill" process, in which the nitride layer is buried 200-1000 angstroms laterally by wet etching.

The submerged cavity is then filled with a second oxide filler, which is then overlaid with the same nitride sidewall, thereby increasing the connection area between the two nitride layers. This increased area maintains the integrity of the nitride-to-nitride connection during the etch of the oxide/nitride/oxide sidewalls and subsequent field oxide formation. A major limitation of this MF ³ R process approach is that the silicon can only be recess-etched to a depth of about 2000 Angstroms, which can lead to insufficient isolation between active regions.

Another method for device isolation is buried oxide (BOX) method. A stress relief oxide layer is grown in the BOX method, followed by deposition of silicon nitride by chemical vapor deposition (CVD). The nitride/oxide stack is then patterned and etched using a standard lithographic process, as in the SWAMI process, followed by a thicker oxide layer, although the CVD oxide layer fills the Etched into recessed silicon areas, the (oxide) layer is uneven because the oxide is deposited in a wide recessed area, thus creating a recess in the CVD oxide layer. To form a flat surface, use a second photoresist (photoresist) pattern, fill the depressions with photoresist (photoresist) material, use a third photoresist (photoresist) to coat over the entire surface, thus producing a fairly flat surface. Etch-back the photoresist and oxide using a photoresist/oxide etchant at the same ratio, removing any remaining photoresist After the solvent is removed, a fairly flat oxide surface is obtained.

There are two main problems with the BOX process approach. The first problem is that the method requires two photolithographic masking steps, adding to the complexity of the process. Second, the BOX method employs a very demanding resist iterative etching process. In fact, the thickness of this spin-on resist depends on the density of the pattern area, and the photoresist layer will be thinner in the denser area. Therefore, after repeated etching by the resist, the etched surface will not be uniform, and the surface of some active regions may be greatly corroded by the etchant.

From the foregoing, it can be seen that there is a need for an isolation process that provides a substantially planar surface at high throughput, substantially free of moat encrochment or stress-induced defects near active regions. In addition, for the isolation process, we require that it can provide a substantially flat surface, and only use a mask once to form a pattern. This improved isolation process provides a flat surface for both narrow and wide grooves between moat areas.

In accordance with the present invention, we provide an isolation process that substantially eliminates or avoids the disadvantages and difficulties associated with existing isolation processes.

According to another aspect of the present invention, there is provided a method for isolating moat regions in a semiconductor substrate separated by narrow and wide grooves. A first field oxide is grown in the wide grooves, and a second field oxide is then deposited on the substrate to fill the narrow grooves and any unfilled portions of the wide grooves.

According to still another feature of the present invention, there is also provided a method of forming an isolation region of an integrated circuit in a silicon substrate. A predetermined portion of the substrate is covered by a pad oxide layer and a first silicon nitride layer. Wide and narrow recesses are etched through the oxide liner layer and first nitride layer to the substrate to form moat regions adjacent to the recesses. A layer of second silicon nitride is deposited on the substrate. Wide grooves are etched to "clear" a gap through the second silicon nitride layer at the bottom of the wide grooves. A first field oxide layer is grown on the area of the substrate exposed by the gap within the wide groove, and a second field oxide layer is deposited to fill the remainder of the narrow and wide grooves. Subsequently, the second field oxide is planarized to a height approximately equal to that of the top edge of the groove, thereby forming isolation regions between the moat regions.

The invention will be described below with reference to the accompanying drawings, beginning with a description of the accompanying drawings, in which,

Figure 1 shows a cross-sectional view of the first step of the present invention, wherein a first nitride layer has a first oxide pad layer below it, and the nitride layer has been patterned with a photoresist , whose exposed portions of nitride, oxide, and silicon have been recess-etched;

Figure 2 shows a cross-sectional view of the second stage of the invention, in which a second thermal oxide layer has been formed and the photoresist has been removed;

Figure 3 shows a cross-sectional view of a third step in the process of the present invention, after deposition of a second nitride layer and a thick oxide sidewall layer;

Fig. 4 has shown the sectional view of the 4th step in the processing method of the present invention, wherein The oxide sidewalls are etched;

Fig. 5 shows a cross-sectional view of the fifth step in the process of the present invention, wherein the remaining sidewall layer has been removed by a wet etch method, and subsequently, a layer of LOCOS field oxide is grown in the silicon exposed gap. things;

Figure 6 shows a cross-sectional view of the sixth step in the process of the present invention, after removal of the first and second silicon oxide layers and deposition of a thick planarized oxide layer;

Figure 7 shows a cross-sectional view of the seventh step in the process of the present invention, wherein planar plasma etching has been carried out on the planar field oxide, and the oxide pad has been removed;

Figure 8 shows a cross-sectional view of a CMOS embodiment of the present invention in which a gate oxide has been formed in the structure of the active region;

Figure 9 shows another embodiment of the present invention corresponding to Figure 1, wherein a polysilicon layer is disposed between the oxide pad layer and the first silicon nitride layer;

Figure 10 shows the structure of Figure 9 after the formation of the second thermal oxide layer.

The application of the preferred embodiment of the present invention can be best understood by referring to Figures 1-8, in which like numerals are used to indicate corresponding like parts in the various figures.

Referring to Fig. 1, a single crystal silicon substrate 10 is shown which has been processed in a tank. To prevent short channel punch through of active transistors, high concentration tanks should be used. A first thermal oxide layer, the oxide pad 12, is grown on the substrate 10 using a thermal process in which silicon dioxide is formed on the surface of the silicon substrate 10. The thickness of the oxide can vary from 200 to 500 Angstroms, preferably 350 Angstroms. After the oxide pad 12 is formed, a first silicon nitride layer 14 is deposited on the oxide pad 12 using a low pressure chemical vapor deposition (LPCVD) method. The thickness of the first silicon nitride layer 14 is generally 1000 to 2000 angstroms, preferably about 1800 angstroms.

After the first silicon nitride layer 14 has been deposited, a photoresist (photoresist) pattern 16 is used to determine the location of the moat area 18 (active area) and expose the groove areas 20a-b and 21a-b. , in the next step these recessed areas will grow field oxide. As will be pointed out, the relatively narrow recessed regions 20a-b and relatively wide recessed regions 21a-b make it difficult to obtain a flat oxide surface using existing isolation processing methods. After photoresist 16 has been deposited and patterned by conventional means, first silicon nitride layer 14 and oxide pad layer 12 are etched according to the pattern of the photoresist. The etch chemical used is preferably CHF ₃ -C ₂ F ₆ , which has a relatively slow etch rate and, therefore, is well controlled by the operator. Of course, it is possible to use other etchants to achieve similar results.

After etching the first nitride layer 14 and the oxide pad layer 12, the silicon substrate 10 can be recessed-etched to form moat regions 18, which will be the active parts of the final device. source area. In the preferred embodiment, silicon is etched to a depth of 3000 to 7500 angstroms, with 5000 angstroms being the preferred depth. The silicon etchant in this preferred embodiment is selected from fluorotrichloromethane (Freon) 11, argon and nitrogen. However, a wide variety of silicon etchants are also possible and are known to those skilled in the art. After the recess etch is complete, the photoresist is removed using well-known photolithography processes.

2 is a cross-sectional view of a semiconductor device that has had a thermal oxide layer 22 formed on the areas of the silicon substrate 10 exposed by recess-etch and on the sides of the oxide pad 12. , forming a continuous oxide capping layer on the silicon substrate 10 . The second thermal oxide layer 22 serves several purposes: one is to round the corners 24 of the recessed region to reduce stress on the corners 24 . The second thermal oxide layer 22 typically has a thickness ranging from 250 to 1000 angstroms, and is preferably about 800 angstroms thick. Since the second thermal oxide layer 22 is relatively thin, there is little loss of boron from the P-well to the growing thermal oxide.

It is worth pointing out that the growth of the second thermal oxide layer 22 on the silicon substrate 10 consumes silicon due to the formation of silicon oxide. The loss of silicon reduces the width of the active moat region 18 . However, the amount of silicon lost during silicon dioxide growth is only 45 percent of the thickness of the grown oxide, so if the width of the grown second thermal oxide layer 22 is 800 angstroms, then each side of the moat area 18 will only reduce the width of the active area by 360 angstroms Spend.

FIG. 3 shows a cross-sectional view of a semiconductor device on which a second silicon nitride layer 26 and a sidewall oxide layer 28 have been deposited by a chemical vapor deposition (CVD) process. The thickness of the second silicon nitride layer 26 is preferably in the range of 500 to 1000 angstroms, generally about 800 angstroms. The thickness of the sidewall oxide layer 28 preferably falls within the range of 4000 to 8000 angstroms, generally 5000 angstroms. It must be pointed out that the thickness of the sidewall oxide layer 28 is much thicker than the original oxide layer, and the selected thickness of the sidewall oxide layer 28 should be enough to fill up the narrow groove regions 20a and 20b, but not to fill up Wide groove regions 21a and 21b. At the narrow recess regions 20a and 20b where the sidewall oxide 28 fills, a small recess 30 will be formed. In the wide recess regions 21a and 21b, the opposite sidewalls of the sidewall oxide are not brought together, leaving a deep recess 32 that will not be filled. The distance between the bottom of the deep recess 32 and the bottom of the corresponding wide recess region 21 a or b should be approximately equal to the thickness of the sidewall oxide layer 28 .

Figure 4 shows a semiconductor device after vertical etching of the sidewall oxide layer 28, the second silicon nitride layer 26 and the second thermal oxide layer 22 using an anisotropic oxide/nitride etching method sectional view of the . In the wide groove regions 21a and 21b, the above three layers are all removed from under the deep recess 32 with an etchant, whereby the silicon substrate 10 is exposed through the slits 34 and 35 . Although it is not necessary to remove the second thermal oxide layer 22 as shown in FIG. 4, it is often removed in practice because the sidewall etch cannot be controlled precisely enough to remove only the second silicon nitride layer 26. . The anisotropic nature of this etch leaves sidewall oxide layer 28 on the sidewalls of wide recess regions 21a-b, leaving a width equal to 80% of the sum of the thicknesses of etched layers 28, 26 and 22. % to 100%. The sidewalls may be etched using the same etch gas, a mixture of CHF ₃ and C ₂ F ₆ , as used for the first nitride layer 14 and the oxide pad layer 12 . Again, other etchants known to those skilled in the art may be sufficient in place of the suggested etchants.

To ensure that all of the nitride is removed from the gap 34, the anisotropic etching process also removes part of the surface of the first silicon nitride layer 14. Therefore, the first silicon nitride layer 14 should be sufficient thick enough to leave about 1000 Angstroms of nitride after sidewall etch. It is important to prevent removal of the nitride from the corners 36 of the sidewalls of the recessed regions 20a-b and 21a-b during etching. In the present invention, the same process for preventing nitride removal as used in MFR can also be used.

The second silicon nitride layer 26 will not be removed from the narrow recess regions 20a and b when the sidewall etch is performed, nor will the etch remove the nitride layer 38 around the trenches 34 and 35 . The thickness of the sidewall oxide layer 28 is selected such that the narrow groove regions 20 a and b can be completely covered by the sidewall oxide layer 28 after the sidewall is etched.

Figure 5 is a cross-sectional view of a semiconductor device whose remaining sidewall oxide layer 28 has been removed from the second silicon nitride layer 26 by wet etching, at the bottom of the wide recess regions 21a-21b A thick and wide thermal field oxide region 40 has grown. It is best to use diluted HF solution for etching chemicals, and the concentration of HF solution is preferably 10%. The wet etch does not affect silicon nitride layers 14 and 26 , or the silicon exposed by gaps 34 and 35 . After the wet etch, wide thermal field oxide regions 40 are grown in gaps 34 and 35 using a LOCOS (Local Oxidation of Silicon) process. Thermal field oxide will not grow on silicon nitride layers 14 and 26 , and thus wide thermal field oxide region 40 is confined to gaps 34 and 35 . The thickness of the wide thermal field oxide region is selected in this way: the upper surface of the wide thermal field oxide region 40 should be substantially on the same plane as the original upper surface of the silicon substrate 10, and its thickness can be in the range of 6000 to 15000 Angstrom range, generally about 10,000 Angstroms thick.

It should also be noted that in some cases the wide groove region 21a has an intermediate width, so that only a small gap 34 is opened when the sidewall is etched. In this case, as shown in FIG. 5, the thickness of the wide thermal field oxide region 40 will be smaller than that obtained in the much wider wide groove region 21b.

As can be seen in FIG. 5 , a wide thermal field oxide region 40 grows under the edge of the nitride layer 38 around it, forming a "bird's beak" 42 . The thickness of the sidewall oxide layer 28 should be selected by comparison with the thickness of the grown wide thermal field oxide region 40 so that the "bird's beak" 42 does not As far as the top edge of the moat area 18 is concerned, it is thus not possible to reduce the active area width of the moat area 18 at those places.

Figure 6 shows a cross-sectional view of a semiconductor device from which the nitride layers 14 and 26 have been removed and on which surface 1 a planarized field oxide layer 44 has been deposited. The nitride layers 14 and 26 can be removed from the surface using hot phosphoric acid ( _H3PO4 at 160°C) or other _suitable chemical solution. The planar field oxide layer 44 is deposited using a chemical vapor deposition (CVD) process in which the thickness of the oxide on the vertical walls grows at the same rate as the thickness of the oxide on the horizontal walls. The oxide thickness is typically 10,000 Angstroms, but can also fall within the range of 8,000-15,000 Angstroms. The thickness of the planar field oxide layer 44 is selected to be sufficiently large so that the oxide on the sidewalls of the recessed regions 20a-b and 21a-b can grow together to fill the regions 20a-b and 21a-b.

Some small depressions 46 may be left on the top surface of the field oxide layer 44 that has been flattened. If necessary, a photoresist layer (not shown) can be added on the top surface of the field oxide layer 44 that has been flattened. out) to further smooth the surface.

7 shows a cross-sectional view of a semiconductor device that has been planarized by plasma etching to remove the planarized field oxide layer 44 and the underlying thermal oxide pad 12 above the upper surface of the moat region 18 . To reiterate, _a mixture of _CHF3 and _C2F6 could be used, or other suitable etchant could be used instead. To ensure that all of the oxide pad layer 12 is removed, a short wet or dry etch may be added at the end of this step. The present structure is readily and conveniently fabricated into an active device 3 using processes well known in the art. As an example, the gate approach of CMOS is described below, although the different steps of other processes, such as bipolar, can also be used in conjunction with the present invention.

FIG. 8 is a cross-sectional view of a semiconductor that has had a gate oxide 48 grown on the moat region 18 to form a CMOS gate. The thickness of the gate oxide 48 can vary from 50 to 250 angstroms, and a thickness of 250 angstroms is generally preferred. After the gate oxide 48 is grown, the process next deposits the material (typically polysilicon) to form the transistor grid. In a different embodiment of the present invention, an oxide pre-gate (Pregate Oxide, not shown) with a thickness of 100-500 angstroms can be grown first, and then it is grown on the gate oxide 48 Removed before to prevent Kooi effect.

Here, it is necessary to point out that the upper surface of the planarized field oxide layer 44 in the groove regions 20a-b and 21a-b is relatively smooth, and this smoothness (the surface) ensures that in the next step The deposited gate material will not crack at the unevenness of the surface (steps in surface). In addition, the flat surface eliminates the creation of shorting wires in the gate material that remain after a highly anisotropic etch used to define the gate boundaries.

Another important feature of the present invention is that the stress-induced silicon structural defects on the sidewalls of the recessed regions 20a-b or 21a-b are minimized. After the deposition of the planarized oxide region layer 44, the only high temperature heat treatment performed is to grow the gate oxide 48 followed by annealing the source/drain implants (not shown). If the recessed areas 20a-b or 21a-b are completely filled by thermal oxidation, many defects will be generated. This is because the concentration used in the tank processing (Tank Processing) is higher. A high concentration of n-wells (n-well) and P-wells (P-Well) will provide sufficient concentration on the sidewalls of the recessed regions 20a-b or 21a-b, and will also prevent interference with the active transistor channel Parallel parasitic leakage. Also, as mentioned in conjunction with FIG. 2, the loss of boron from the P-Well to the growing second thermal oxide layer 22 will be minimal because the second thermal oxide layer The thickness of 22 is very small. However, after the recessetch, a boron channel stop implant can be performed along the sidewalls and at the bottom of the recess regions 20a-b and 21a-b if necessary to increase the threshold voltage of the thick regions.

Figure 9 shows a different embodiment of the present invention in which an optional polysilicon layer 50 is deposited between the oxide liner layer 12 and the first silicon nitride layer 14 to protect the silicon substrate during planar etching 10. Using an etch method that is selective to polysilicon, i.e., one that etches polysilicon at a low rate, the planar etch will terminate at the selectable polysilicon The crystalline silicon layer 50 will not be etched into the silicon substrate 10 .

An additional polysilicon layer may be necessary if the planar etch cannot be controlled precisely enough. It should be noted that if a polysilicon layer 50 is used, as shown in FIG. 10, as described with reference to FIG. and the side walls of 21a-b. Since the polysilicon layer 50 is undoped and the silicon substrate 10 is relatively more doped, the oxidation conditions can be selected so that the etching rate of the polysilicon layer 50 is lower than that of the silicon substrate 10 . This forms an extended polysilicon cap 52 on the edge of the top of the silicon moat region 18, thereby protecting it from planar etch. Since the growth of the second thermal oxide layer 22 will also consume part of the extension of the extended polysilicon cap 52, the thickness of the optional polysilicon layer 50 should be selected such that after the second thermal oxide layer 22 grows Sufficient polysilicon is left at the edges (of layer 50 ) so as not to crack the polysilicon layer 50 at the edges of the extended polysilicon cap 52 .

Therefore, the present invention has the above-mentioned and many other advantages, and it will be obvious to those skilled in the art that the present invention can be widely improved and variously modified, except as set forth in the appended claims. Otherwise, the scope of the present invention will not be limited in any way.

Claims (7)

1, a kind of method of making isolated area on a surface of semiconductor piece comprises:

Described surface etching at described semiconductor piece goes out first and second grooves, each groove has a sidewall and a bottom, the part of described surface outside described first and second grooves is defined as an active area, and the width of described first groove is greater than the width of described second groove;

On described active area and along the sidewall and the bottom of described groove, form an oxidation mask;

Form a masking layer on described oxidation mask, described masking layer is thinner than the part near this recess sidewall near the part at the described first groove center;

The described masking layer of etching, thereby the thin part of removing masking layer in described first groove, and in described first groove, leave the part masking layer near the recess sidewall place, and all leave described masking layer on the whole width of described second groove,

Remove described be positioned at described first bottom portion of groove not by described masking layer near the part at the position that residual fraction covered of recess sidewall, oxidation mask;

Remove the residual fraction of described masking layer;

Described first bottom portion of groove is positioned at the partial oxidation at the position of removing the oxidation barrier layer, to form first oxide layer at this place;

After described oxidation step, deposit one second oxide layer on described active area and in described first and second grooves; With

Second oxide layer on the described active area of etching.

2, the step of the method for claim 1, wherein removing described masking layer residual fraction was carried out before described oxidation step.

3, the method for claim 1, wherein described oxidation barrier layer comprises silicon nitride.

4, the method for claim 1, wherein described masking layer comprises silicon dioxide.

5, the method for claim 1, it also comprises: the impurity that will be used to form the channel cutoff district after the step of the described groove of etching injects the sidewall of described first and second grooves.

6, also second oxide layer on the described groove of etching of the step of second oxide layer on the method for claim 1, wherein described etching active area makes the surface coplane roughly of the surface that remains in second oxide layer in the described groove and described active area.

7, the method for claim 1, it also comprises:

After the step of described second oxide layer of deposit, the shape film is applied in deposit one on described second oxide layer, and, the step of described second oxide layer of etching comprises the described deposited shape film and second oxide layer on described active area of etching and the groove, makes the surface coplane roughly of the surface remain in second oxide layer in the described groove and described active area.

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