CN100556166C - The method and system of protected data in mobile communication process - Google Patents

Abstract

The invention discloses a kind of in mobile communication process the method and system of protected data, comprise mobile multimedia processor, decipher the cryptographic algorithm in the described mobile multimedia chip hardware.Described mobile multimedia processor uses the data in the algorithm decryption software of described deciphering.Described mobile multimedia processor is deciphered the instruction of described cryptographic algorithm when instruction entry instruction high-speed cache.Described mobile multimedia processor is carried out the also result of the described Hash operation of verification of Hash operation to described data decryption, to protect described data decryption.

Description

Method and system for protecting data during mobile communication

technical field

The present invention relates to a mobile multimedia processor, and more particularly, the present invention relates to a digital rights management method and system in a mobile multimedia processor.

Background technique

Mobile communications have changed the way people communicate, and mobile phones have transformed from a luxury item to an essential part of people's daily lives. The use of mobile phones depends on the social situation and is not restricted by location and technology. At present, the voice connection has met the basic needs of daily communication, and the mobile voice connection is continuously integrated into every aspect of daily life, and the next step of the mobile communication revolution will be the integrated mobile multimedia application using the mobile Internet.

The third-generation (3G) cellular network that can provide a variety of high-speed access technologies, as well as mobile phones specially designed to apply these technologies, meet people's needs for TV and audio applications that support the use of advanced compression standards, high-resolution gaming applications, Music interface, peripheral interface support and other integrated multimedia application requirements. As chip designers use compression techniques and higher bandwidth to transmit more information, processing requirements also increase. For example, 3G wireless applications support bit rates between 384k/s and 2M/s, which allows chip designers to provide wireless systems with multimedia performance, higher quality, lower interference and larger coverage areas.

As mobile multimedia services become more popular, factors such as power consumption, cost-effective network performance, and quality of service will become more important to telecom operators. Meticulous network planning and deployment, improvements in transmission methods, improvements in receiver technology and chip integration solutions can make the above goals achievable. In this regard, operators need a technology that can provide higher downlink throughput for mobile multimedia applications, so as to provide consumers of mobile multimedia application services with better QoS performance and speed. Currently, mobile multimedia processors have not fully exploited the role of system-on-a-chip (SOC) integration to provide a better overall system solution for today's mobile handsets. For example, existing mobile processors can use multiple hardware accelerators to support multiple multimedia applications, which will significantly increase power consumption, implementation complexity, footprint of the mobile processor, and final volume of the mobile terminal. Content owners insist on digital rights management (DRM) to keep the associated algorithm or part of the algorithm secret. Nonetheless, regular updates and revisions are required.

Other limitations and drawbacks of the prior art will be apparent to those of ordinary skill in the art when comparing the system of the present invention which will be described later with reference to the accompanying drawings.

Contents of the invention

The present invention provides a system and/or method for digital rights management in a mobile multimedia chip, introduced with at least one accompanying drawing, and fully described in the claims.

According to one aspect of the present invention, a method for protecting data during mobile communication is provided, the method comprising:

Decrypt the encrypted algorithm in the multimedia mobile processor hardware;

decrypting data within software processed by the mobile multimedia processor using the decrypted algorithm;

An unused memory row is inserted between the decrypted data and the decrypted algorithm to prevent corruption of the decrypted data.

Advantageously, the method further comprises decrypting instructions of said encrypted algorithm when said instructions enter an instruction cache.

Preferably, the method also includes:

protecting the decrypted data by hashing the decrypted data;

Verify the result of the hash operation.

Advantageously, the method further comprises: storing a decryption key of said encrypted algorithm in said mobile multimedia processor hardware in write-only form.

Advantageously, the method further comprises decrypting said encrypted algorithm in said mobile multimedia processor hardware using said decryption key.

Advantageously, the method further comprises: concealing the location of said stored decryption key.

Advantageously, said method further comprises disabling at least one interrupt prior to said decrypting said encrypted algorithm.

Advantageously, the method further comprises enabling at least one interrupt after said decrypting said encrypted algorithm.

According to one aspect of the present invention, there is provided a machine-readable memory, wherein the stored computer program comprises at least one code segment for protecting data during mobile communication, said at least one code segment being executable by a machine to enable said machine Perform the following steps:

Decrypt the encryption algorithm in the multimedia mobile processor hardware;

Data within software processed by the mobile multimedia processor is decrypted using the decrypted algorithm.

Advantageously, said machine readable memory further comprises code to decrypt instructions for said algorithm when said instructions enter an instruction cache.

Advantageously, said machine readable storage further comprises code for protecting said decrypted data by performing a hash operation on said decrypted data and verifying a result of said hash operation.

Advantageously, said machine-readable memory further comprises code for storing a decryption key of said encryption algorithm in said mobile multimedia processor hardware in write-only form.

Advantageously, said machine readable memory further comprises code for decrypting said encryption algorithm in said mobile multimedia processor hardware using said decryption key.

Advantageously, said machine readable memory further comprises code for concealing the location of said stored decryption key.

Advantageously, said machine readable memory further comprises code for disabling at least one interrupt prior to said decryption of said encryption algorithm.

Advantageously, said machine readable memory further comprises code for enabling at least one interrupt after said decryption of said encryption algorithm.

Advantageously, said machine readable memory further comprises code for inserting an unused memory line between said decrypted data and said decryption algorithm to prevent corruption of said decrypted data.

According to one aspect of the present invention, a system for protecting data during mobile communication is provided, the system comprising:

a mobile multimedia processor, decrypting an encrypted algorithm in said mobile multimedia processor hardware;

said mobile multimedia processor decrypts data within software processed by said mobile multimedia processor using said decrypted algorithm and inserts an unused memory between said decrypted data and said decrypted algorithm line to prevent corruption of the decrypted data.

Advantageously, said mobile multimedia processor decrypts instructions of said encrypted algorithm when said instructions enter an instruction cache.

Advantageously, said mobile multimedia processor protects said decrypted data by performing a hash operation on said decrypted data, and checks a result of said hash operation.

Advantageously, said mobile multimedia processor stores a decryption key of said encrypted algorithm in write-only form in said mobile multimedia processor hardware.

Advantageously, said mobile multimedia processor decrypts said encrypted algorithm in said mobile multimedia processor hardware using said decryption key.

Advantageously, said mobile multimedia processor conceals the location of said stored decryption key.

Advantageously, said mobile multimedia processor disables at least one interrupt prior to said decryption of said encrypted algorithm.

Advantageously, said mobile multimedia processor enables at least one interrupt after said decryption of said encrypted algorithm.

These and other advantages, objects and innovative features of the present invention, together with details of the described embodiments, will be fully understood when taken in conjunction with the following description and accompanying drawings.

Description of drawings

FIG. 1A is a schematic structural diagram of a mobile multimedia system according to an embodiment of the present invention;

FIG. 1B is a schematic structural diagram of a mobile multimedia system according to an embodiment of the present invention;

Fig. 2 is a schematic structural diagram of a code decryption system according to an embodiment of the present invention;

Fig. 3 is a schematic structural diagram of a code decryption system according to an embodiment of the present invention;

Figure 4 is a flowchart of program flow in the memory stack when executing encrypted code according to one embodiment of the present invention;

FIG. 5 is a flow chart of the steps of protecting data during mobile communication according to one embodiment of the present invention.

Detailed ways

According to one embodiment of the present invention, a method and system for protecting data in mobile communications includes a mobile multimedia processor decrypting an encrypted algorithm within the mobile multimedia processor. The mobile multimedia processor can decrypt the data in software using the decrypted algorithm. The mobile multimedia processor can decrypt the encrypted algorithm's instructions when the instructions enter the instruction cache. The mobile multimedia processor can protect the code in plain text format by hashing it, and check the result of the hash operation in the mobile multimedia processor. The use of encrypted codes protects the codes in plain text form from modification.

FIG. 1A is a schematic structural diagram of a mobile multimedia system according to an embodiment of the present invention. As shown in Figure 1A, a mobile multimedia system 105 includes a mobile multimedia device 105a, a TV 101h, a PC 101k, an external camera 101m, an external memory 101n and an external LCD display 101p. The mobile multimedia device 105a may be a cellular telephone or other handheld communication device. The mobile multimedia device 105a may include a mobile multimedia processor (MMP) 101a, an antenna 101d, an audio module 101s, a radio frequency (RF) module 101e, a baseband processing module 101f, an LCD display 101b, a keyboard 101c, and a camera 101g.

The MMP 101a may contain appropriate circuitry, logic and/or code for video and/or multimedia processing for the mobile multimedia device 105a. The MMP 101a may further include a plurality of integrated interfaces for supporting one or more external devices connected to the mobile multimedia device 105a. For example, MMP 101a may support connections to TV 101h, PC 101k, external camera 101m, external memory 101n, and external LCD display 101p.

During operation, the mobile multimedia device can receive signals through the antenna 101d. The received signal may be processed by the RF module 101e, and the RF signal may be converted to baseband by the baseband processing module 101f. The baseband signal is then processed by MMP 101a. Audio and/or video signals may also be from/to integrated camera 101g, TV 101h, PC 101k and/or external camera 101m. During signal processing, the MMP 101a can use the external memory 101n to store processed data. The processed audio data is sent to the audio module 101s, and the processed video data is sent to eg TV 101h, LCD 101b or external LCD 101p. The keyboard 101c may be used to transmit processing commands and/or other data required by the MMP 101a for processing audio or video data.

FIG. 1B is a structural diagram of a mobile multimedia processor according to an embodiment of the present invention. As shown in FIG. 1B, the mobile multimedia processor 102 may contain suitable logic, circuitry and/or code for performing video and/or multimedia processing for a handheld multimedia product. For example, the mobile multimedia processor 102 may be designed/optimized for video recording/playback, mobile TV, and 3D mobile gaming by using integrated peripherals and video processing cores. Mobile multimedia processor 102 includes video processing core 103, RAM 104, analog module 106, direct memory access (DMA) controller 163, audio interface (I/F) 142, memory stick I/F 144, SD card I/F 146, JTAG I/F 148 , TV output I/F 150 , USB I/F 152 , camera I/F 154 , host I/F 129 and built-in integrated circuit (I ² C) I/F 156 . Mobile multimedia processor 102 may further include serial peripheral interface (SPI) 157, universal asynchronous receiver/transmitter (UART) I/F 159, general purpose input/output (GPIO) pins 164, display controller 162, external memory I/F 158 and a second external memory I/F 160 .

Video processing core 103 may include suitable circuitry, logic and/or code for performing video processing of data. RAM 104 may include appropriate logic and/or code for storing on-chip data, such as video data. In one embodiment of the invention, RAM 104 may be used to store 10Mb of on-chip data, for example. The size of the on-chip RAM 104 is related to cost or other factors such as chip size.

The analog module 106 may include a switch mode power supply (SMPS) module and a phase locked loop (PPL) module. Additionally, the analog module 106 may include an on-chip SMPS controller for generating its core voltage. The core voltage can be software programmed to further control power management, eg, based on speed requirements on the mobile multimedia processor 102 .

In one embodiment of the present invention, the operating range of the core voltage is between 0.8V-1.2V under normal conditions, and this value drops to about 0.6V in sleep mode. The analog module 106 may also include multiple phase-locked loops for generating 195kHz-200MHz clocks for external devices, for example. Depending on the type of application, other voltage values and clock rates may also be used. The mobile multimedia processor 102 may include multiple operating power modes, such as run, standby, sleep, and power-down modes. According to one embodiment of the present invention, the mobile multimedia processor 102 may include a bypass mode that allows the host to Access memory-mapped peripherals. In the bypass mode, the mobile multimedia processor 102 can directly control the display during normal operation. The host can maintain the displayed content in standby mode.

The audio module 108 may include suitable logic, circuitry, and/or code for communicating via, for example, an inter-integrated circuit audio (I ² S) bus, pulse code modulation (PCM) or audio codec (AC'97) interface 142 or other suitable The interface communicates with the mobile multimedia processor 102. Where AC'97 and/or ^I2S interfaces are used, either in master or slave mode, appropriate audio controllers, processors and/or circuitry may be used to provide AC'97 and/or I2S interfaces, respectively ² S audio output. In the case of a PCM interface, appropriate audio controllers, processors and/or circuits may be used to enable voice or high-quality stereo audio input and output. PCM audio controllers, processors and/or circuits may include separate transmit and receive first-in-first-out (FIFO) buffers and use DMA to further reduce processor overhead. The audio module 108 may also include audio-in, audio-out ports, and speaker/microphone ports (not shown in FIG. 1B ).

The mobile multimedia device 100 may include at least one portable memory input/output (I/O) module. In this regard, the memory stick module 110 may include suitable logic, circuitry and/or code for communicating with the mobile multimedia processor 102 via the memory stick support interface 144 . SD card module 112 may include suitable logic, circuitry and/or code for communicating with mobile multimedia processor 102 via SD input/output (I/O) interface 146 . A multimedia card (MMC) may also be used to communicate with the mobile multimedia processor 102 through, for example, SD input/output (I/O) interface 146 . Mobile multimedia device 100 may include other portable memory I/O modules, such as xD I/O cards.

The debug module 114 may include suitable logic, circuitry, and/or code for communicating with the mobile multimedia processor 102 through, for example, a Joint Test Action Group (JTAG) interface 148 . The debug module 114 can be used to access the address space of the mobile multimedia processor 102 and can perform boundary scan through the emulation interface. Other test access ports (TAPs) may also be used by the mobile multimedia device 100 . Phase Alternate Line (PAL)/National Television Standards Committee (NTSC) TV out I/F 150 can be used to communicate with a TV, Universal Serial Bus (USB) 1.1 or other variant, slave port I/F 152 can be used to communicate with e.g. The PC communicates. Cameras 120 and/or 122 may include suitable logic, circuitry and/or code for communicating with mobile multimedia processor 102 via, for example, multi-format raw CCIR 601 camera interface 154. The camera I/F 154 may interface the mobile multimedia processor 102 with the mobile TV head-end using functions such as windowing and sub-sampling.

Mobile multimedia processor 102 may also include multiple serial interfaces such as USB I/F 152, Inter-Integrated Circuit (I ² C) Host I/F 156, Serial Peripheral Interface (SPI) 157, and Bluetooth or IrDA Universal Asynchronous Receiver/Transmitter (UART) I/F 159. I ² C master interface 156 may include appropriate circuitry, logic, and/or code for controlling the image sensor, and may be used to interface with smart batteries and other peripherals. SPI master interface 157 may include appropriate circuitry, logic and/or code for controlling the image sensor. Dual chip select can be used when using interrupts or when operating in polled mode through the DMA controller 163 . In addition, the mobile multimedia processor 102 may also include a plurality of general purpose I/O (GPIO) pins 164 for user-defined I/O or connection to other internal peripherals. Display controller 162 may include appropriate circuitry, logic and/or code to support multiple displays at XGA resolution, for example, and to process 8/9/16/21 bit video data.

The baseband flash memory 124 may be used to receive data from the mobile multimedia processor 102 through, for example, an 8/16 bit parallel host interface 129 . The host interface 129 can be used to provide two channels with independent address and data registers through which the host processor can directly read and/or write to the memory space of the mobile multimedia processor 102 . The baseband processing module 126 may contain suitable logic, circuitry and/or code for converting RF signals to baseband signals and communicating the processed baseband signals to the mobile multimedia processor 102 via, for example, the host interface 129 . The RF processing module 130 may include suitable logic, circuitry and/or code for receiving signals via the antenna 132 and communicating the RF signals to the baseband processing module 126 . Host interface 129 may include dual software channels with power active bypass mode.

The main LCD 134 is used to receive data from the mobile multimedia processor 102 via the display controller 162, or from the second external memory interface 160, for example. Display controller 162 may include appropriate logic, circuitry, and/or code for driving an internal TV output function, or interfaced into an LCD. The display controller 162 can be used to support a certain range of screen buffer formats, use direct memory access (DMA) to directly access the buffer, and increase the video processing efficiency of the video processing core 103 . Display controller 162 can generate NTSC and PAL raster formats to drive TV output. Display controller 162 may also support other formats, such as SECAM.

In one embodiment of the present invention, display controller 162 may be used to support a variety of displays, eg, an interlaced display such as a TV, and/or a non-interlaced display such as an LCD. The display controller 162 may also identify and transfer the display type to the DMA controller 163 . In this regard, the DMA controller 163 can capture video data in an interlaced or non-interlaced manner, and then send it to an interlaced or non-interlaced display connected to the mobile multimedia processor 102 via the display controller 162 .

Secondary LCD 136 may include suitable logic, circuitry and/or code for communicating with mobile multimedia processor 102 via, for example, a second external memory interface. The mobile multimedia processor 102 may include an RGB external data bus. The mobile multimedia processor 102 may adjust the image output using pixel-level interpolation and a settable refresh rate.

Optional flash memory 138 may include suitable logic, circuitry and/or code for communicating with mobile multimedia processor 102 through, for example, external memory interface 158 . Optional SDRAM 140 may include suitable logic, circuitry and/or code for receiving data from mobile multimedia processor 102 through, for example, external memory interface 158. Mobile multimedia processor 102 may use external memory I/F 158 to connect to, for example, external SDRAM 140, SRAM, flash memory 138, and/or external peripherals. Control and timing information for SDRAM 140 and other asynchronous devices can be configured by mobile multimedia processor 102.

The mobile multimedia processor 102 may further include a secondary memory interface 160 to connect to, for example, a memory-mapped LCD and external peripherals. Secondary memory interface 160 may include suitable circuitry, logic, and/or code for connecting mobile multimedia processor 102 to low-speed devices without compromising external memory access speeds. Secondary memory interface 160 may provide, for example, 16 data lines, 6 chip select/address lines, and programmable bus timing for use in setup, and access and hold times. The mobile multimedia processor 102 can provide support for NAND/NOR flash memory, including, for example, NAND boot and high-speed direct memory access (DMA).

During operation, the mobile multimedia processor 102 may provide multiple display formats for the display of the processed video data. For example, interlaced and/or non-interlaced external displays may be coupled to mobile multimedia processor 102 through display controller 162 . The display controller 162 can transfer the external display type to the DMA controller 163 . The DMA controller 163 then accesses the on-chip RAM 104 and retrieves the processed video data in either interlaced or non-interlaced format corresponding to the type of external display.

Fig. 2 is a schematic structural diagram of a code decryption system according to an embodiment of the present invention. A memory module 202 , an instruction fetch module 204 , a decryption module 206 , a decoder module 208 , a status register 210 , a read only memory (ROM) 212 and a decision module 214 are shown in FIG. 2 .

The memory module 202 may include suitable logic, circuitry and/or code for storing data and/or instructions for use. The memory module 202 is connected with the instruction acquisition module 204 . Instruction fetching module 204 may include suitable logic, circuitry, and/or code for fetching instructions from memory module 202 and storing the instructions in memory module 202 and/or ROM 212. Decryption module 206 may include suitable logic, circuitry and/or code for receiving instructions and/or data from instruction fetching module 204 and ROM 212. Decryption module 206 may be used to modify the order of received data and send a set of instructions and/or data to decoder module 208 . Decoder module 208 may include suitable logic, circuitry, and/or code for receiving data and/or instructions from decryption module 206 and executing them.

Status register 210 may include suitable logic, circuitry, and/or code for receiving, storing, and/or sending data and/or instructions to ROM 212. Status register 210 may also hold addresses of memory locations and data from or to memory. ROM 212 may include suitable logic, circuitry, and/or code for receiving a set of data and/or instructions from instruction fetch module 204 and status register 210. ROM 212 may be used to store and/or transmit data to decryption module 206. The decision module 214 may include suitable logic, circuitry and/or code for determining whether the value of the status register 210 is greater than zero. If the value of status register 210 is greater than 0, stepping will be disabled.

Multiple bits may be added to status register 210, for example 3 bits, E2-E0. If the value of these 3 bits is equal to 0, the processor is working in normal operation mode. If the value of these three bits is non-zero, these three values can define one of the seven encryption modes. When the code is fed back to the instruction decode module 208, it will be decrypted. In this way, the code in plain text format is not visible in the memory module 202 or the trace cache. To prevent stepping through the code, stepping through is disabled. Operations can be tracked by changes in the contents of the status register 210 instead of by the instructions executed. Due to the limited size of ROM 212, the one-time key in the encrypted code may have several cycles. The relocation of the code is related to the number of low address bits used in the key. Protected Digital Rights Management (DRM) encryption algorithms can be embedded along with CPRM device keys. The encryption algorithm can also be used to move the code, adding additional instructions to hide the location of the device's second key and prevent attacks because hackers can obtain multiple copies of the device key. According to one embodiment of the invention, the encryption algorithm can also be used to protect code against tempering by hashing the algorithm itself and verifying the results of the operation at various points during the operation. test to achieve.

Fig. 3 is a schematic structural diagram of a code decryption system according to an embodiment of the present invention. A command decryption module 302, a plurality of multiplexers MUX 304 and MUX 308, an instruction cache module 306, an instruction fetch module 310 and an instruction decoder module 312 are shown in FIG.

The command decryption module 302 may include suitable logic, circuitry and/or code for receiving data, such as 256 bytes of data and/or instructions, and decrypting the code and/or data in a secure mode of operation. MUX 304 may include suitable logic, circuitry and/or code for selecting between encrypted instructions and/or data from command decryption module 302 and decrypted instructions and/or data. When MUX 304 is available in secure mode, MUX 304 selects signals from command decryption module 302. Instruction cache module 306 may include suitable logic, circuitry, and/or code for temporarily storing instructions for fast access by instruction fetch module 310 . The data stored in the instruction cache module 306 may be 256 bytes wide data. MUX 308 may include suitable logic, circuitry and/or code for selecting between instructions and/or data from instruction cache module 306 and directly from MUX 304. The instruction fetch module 310 may include suitable logic, circuitry and/or code for fetching instructions from memory. The instruction decoder module 312 may include suitable logic, circuitry and/or code for receiving data and/or instructions from the instruction fetch module 310 and decoding the data and/or instructions.

The command decryption module 302 can handle mixed codes in encrypted and plain text format. Code in plain text format handles interrupts. A plain text copy of the encrypted code is not available because the instructions and/or data stored in the instruction cache module 306 can only be read by the instruction decoder module 312 . During code decryption, sending data lines to code cache module 306 and/or instruction decoder module 312 will cease until code decryption is complete. The code will be decrypted in the secure host and stored in a device. The key used to decrypt the code is stored in non-volatile RAM which is only writeable once and readable by command decryption module 302 .

FIG. 4 is a flowchart of the program flow in the memory stack when executing encrypted code according to one embodiment of the present invention. A memory stack 400 , a normal text function 420 , a jump2crypted function 422 , a run_crypted function 424 and an encryption function 426 are shown in FIG. 4 .

Plain text function 420 may include appropriate logic and/or code for accessing encryption function 426 . The jump2crypted function 422 may include appropriate logic and/or code to switch between decrypting the code and calling the run_crypted function 424 . The jump2crypted function 422 may be used as a wrapper around the run_crypted function 424 . The run_crypted function 424 may include appropriate logic and/or code for invoking the requested encryption function 426 . Encryption function 426 cannot be called directly from plain text format code because there may not be a switch to code decryption. When several different segments of the encrypted code are used, each segment may request its own jump2crypted function 422 and run_crypted function 424 . The encryption function 426 cannot directly call the text function, because it may not have been switched out from code decryption.

At step 402 , plain text function 420 may access encryption function 426 by calling jump2crypted function 422 . At step 404 , the jump2crypted function 422 acting as a wrapper for the run_crypted function 424 may switch to code encryption and call the run_crypted function 424 . At step 406 , the run_crypted function 424 calls the requested encryption function 426 . Encryption functions cannot be called directly from plain text format code because there may not be a switch to code decryption. When several different segments of the encrypted code are used, each segment may request its own jump2crypted function 422 and run_crypted function 424 . However, in step 408, after the encryption function 426 is executed, it will return to the run_crypted function 424. At step 410 , the run_crypted function 424 will switch out of code decryption and return control to the jump2crypted function 422 . At step 412 , the jump2crypted function 422 will return control to the call to the normal text format function 420 .

According to an embodiment of the present invention, when the system is running in a secure mode, the stored encrypted code can be dynamically decrypted during execution. The code decryption used in secure mode works on memory lines, for example 32 bytes wide. These storage lines do not contain data or code in plain text format, as this could lead to erroneous code decryption during runtime. A tool such as MetaWare( ^TM) can be used to separate plain text code, encrypted code and data in memory. The required amount of storage can be automatically allocated for each type of code using a linker such as a MetaWare( ^TM) linker.

To enable/disable code decryption in a controlled manner, a real-time interrupt instruction (rti) can be used to access the memory segment containing the encrypted code. Encryption functions can be used to directly call other encryption functions, but plain text format functions cannot be called. Code encryption can be performed within buckets, where each bucket can be in encrypted or plain text format. Code can be encrypted, but data cannot. Encrypted code and data cannot be mixed in the same memory row, such as 32 consecutive addresses starting at a multiple of 32, because the data may change during program execution and change the code decryption. Because the code may not be decrypted properly when using a switch instruction because the required lookup table is stored in the data cache rather than the instruction cache, a branch or predicate instruction can be used instead of the switch instruction. Interrupts will be disabled during the running of encrypted code because they fail to switch to and from code decryption properly. The jump2crypted function 422 may include appropriate logic and/or code to disable any interrupts, while the run_crypted function 424 may include appropriate logic and/or code to restore a previous state of operation.

Constant arrays in encrypted code are not encrypted because they are stored in data registers. Instead of this constant array, a function can be used that returns a constant value by accessing the constant array index. Encryption of the constant array is then achieved by storing the immediate value of the constant using a move or store command.

This code can be adjusted according to the requirements of the security model using a linker such as the metaware linker. For all encrypted codes, separate sections can be defined in the high-level code file. For example, the following code segment can be inserted into the command file, which will generate a special storage area, such as a .cypt file of the required size for the encrypted code.

.dont use ALIGN(32)BLOCK(32):{.=.+32;}>RAM

.crypt? ALIGN(32)BLOCK(32):{*(TYPE text)}＞RAM

Storage.crypt can be arranged by address and generated when encrypted code is present. An unused memory line, such as a 32-byte memory line, is generated between the end of the plain text code and the encrypted code to prevent broken code decryption. For example, the C code stored in the memory space .crypt can be selected and inserted between the program #pragma code(“.crypt) and #pragma code(). When compiling the module containing the encrypted code of the program , the linker switch such as each_function_in_its_own_section will be cut off. You can check whether the encryption code has been moved to the encryption section using a driver selection such as -Hldopt=-m, which can generate a memory map of all sections. A program such as the C program encrypt_code can be used .c to encrypt the code. This program can obtain the start address and end address of the encrypted code in the memory, as well as the memory content in binary format as the program parameter.

Fig. 5 is a flowchart of data protection during mobile communication according to an embodiment of the present invention. As shown in FIG. 5 , the process starts at step 502 . In step 504, the decryption of plain text format codes may be enabled or disabled. At step 506, a hash operation of the plain text format code or the decrypted data is performed and the result is checked to determine whether the plain text format code has been modified. In step 508, the location of the decryption key is concealed. At step 510, the decryption key is stored in hardware or in an encrypted portion of the code in write-only form. At step 512, the algorithm is decrypted using the decryption key. In step 514, the instruction is decrypted as it enters the instruction cache. The instructions of the encryption algorithm may be decrypted using the mobile multimedia processor (MMP) 101a (FIG. 1A) when the instructions enter an instruction cache, such as the instruction cache module 306 (FIG. 3). At step 516, code decryption is switched ON/OFF using at least one interrupt. At step 518, the data will be decrypted in software. Then jump to end step 520 .

According to one embodiment of the present invention, a method and system for protecting data during mobile communication includes a mobile multimedia processor (MMP) 101a (FIG. 1A) that decrypts encrypted algorithms in hardware. A mobile multimedia processor such as MMP 101a can use the decrypted algorithm to decrypt data in software. The mobile multimedia processor (MMP) 101a may decrypt the encrypted algorithm's instructions when the instructions enter an instruction cache, such as instruction cache module 306 . The instruction cache module 306 ( FIG. 3 ) is used to temporarily store instructions for fast access by the instruction fetch module 310 . Data stored in instruction cache module 306 is 256 bytes wide. The mobile multimedia processor, such as MMP 101a, can perform a hash operation on the decrypted data and verify the result of the hash operation, so as to protect the decrypted data.

A mobile multimedia processor, such as the MMP 101a, may store the encrypted algorithm's decryption key in write-only form in hardware. A mobile multimedia processor, such as MMP 101a, can use the stored decryption key to decrypt the encrypted algorithm in hardware. A mobile multimedia processor, such as MMP 101a, can modify the instructions in the encrypted algorithm. A mobile multimedia processor, such as the MMP 101a, may hide the stored decryption or storage location of the DRM key. A mobile multimedia processor, such as MMP 101a, can disable at least one interrupt before decrypting the encrypted algorithm. A mobile multimedia processor, such as MMP 101a, may enable at least one interrupt after decrypting the encrypted algorithm. A mobile multimedia processor, such as MMP 101a, may insert an unused memory line between the decrypted data and the decrypted algorithm to prevent corruption of the decrypted data.

Therefore, the present invention can be realized by hardware, software, or a combination of hardware and software. The invention can be implemented in a centralized fashion in at least one computer system, or in a distributed fashion where different components are distributed over several interconnected computer systems. Any kind of computer system or other device capable of implementing the method of the present invention is applicable. A typical combination of hardware, software and firmware is a general purpose computer system with a computer program that, when loaded and executed, controls the computer system so as to carry out the methods described herein.

The present invention can also be embedded in a computer program product including various features capable of implementing the method, and when the program is loaded into a computer system, the method described in this application can be implemented. The computer program mentioned in this article refers to, for example, a set of instructions expressed in any language, code or symbol, which can directly cause a system with information processing capabilities to perform specific functions, or make a system with A system of information processing capabilities that performs a specific function: a) conversion into another language, code, or symbol; b) reproduction in a different material. However, other implementation methods of computer programs known to those skilled in the art can also be used in the present invention.

The present invention has been described above in conjunction with certain embodiments. Those skilled in the art will know that various changes or equivalent replacements can be made to the present invention without departing from the scope of the present invention. In addition, various modifications to adapt a particular environment or material to the teachings of the invention do not depart from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiments disclosed, but that the invention includes all embodiments falling within the scope of the claims.

This application cites in its entirety and claims US Provisional Patent Application No. 60/652439 (Attorney Docket No. 16433US01) filed February 12, 2005.

This application cites the US Patent Application No.____________ (attorney case No. 16435US02) filed at the same time in its entirety.

Claims (10)

1, a kind of in mobile communication process the method for protected data, it is characterized in that described method comprises:

Encrypted algorithm in the deciphering Multimedia Mobile processor hardware;

Use the data in the software that the algorithm deciphering after the described deciphering handled by described mobile multimedia processor;

Between described algorithm after decrypted data and described deciphering, insert one and do not use storage line, to prevent described damage through decrypted data.

2, method according to claim 1 is characterized in that, described method also comprises: when the instruction entry instruction high-speed cache of described encrypted algorithm, decipher described instruction.

3, method according to claim 1 is characterized in that, described method also comprises:

By to described through decrypted data carry out Hash operate protect described through decrypted data;

The result of the described Hash operation of verification.

4, method according to claim 1 is characterized in that, comprises that also the decruption key with described encrypted algorithm is stored in the described mobile multimedia processor hardware only to write form.

5, method according to claim 4 is characterized in that, described method also comprises: use the decruption key of described storage that the described encrypted algorithm in the described mobile multimedia processor hardware is decrypted.

6, a kind of in mobile communication process the system of protected data, described system comprises:

Mobile multimedia processor is deciphered the encrypted algorithm in the described mobile multimedia processor hardware;

Described mobile multimedia processor uses the data in the software that the algorithm deciphering after the described deciphering handled by described mobile multimedia processor, and between described algorithm after decrypted data and described deciphering, insert one not with storage line to prevent described damage through decrypted data.

7, system according to claim 6 is characterized in that, described mobile multimedia processor is deciphered described instruction when the instruction entry instruction high-speed cache of described encrypted algorithm.

8, system according to claim 6 is characterized in that, described mobile multimedia processor by to described through decrypted data carry out Hash operate protect described through decrypted data, and the result of the described Hash operation of verification.

9, system according to claim 6 is characterized in that, described mobile multimedia processor is stored in the decruption key of described encrypted algorithm in the described mobile multimedia processor hardware only to write form.

10, system according to claim 6 is characterized in that, described mobile multimedia processor uses the decruption key of described storage that the described encrypted algorithm in the described mobile multimedia processor hardware is decrypted.

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