CN100388631C - A Fast Calculation Method of Channel Coding in Mobile Communication - Google Patents

Abstract

The present invention discloses a rapid calculation method for channel codes in mobile communication, which comprises the following procedures that the relation between the initial state of each path output of a channel code encoder and each shift register in the encoder and each path input bit is obtained according to the logic structure of the channel code encoder used at present; each function representation part of each obtained path output is respectively stored, and a corresponding lookup table is respectively generated for each storage part; when a code is calculated, each code is firstly obtained by all functions of an ith path of output of the channel code encoder, which represent the present calculation, according to each corresponding lookup table, and then modular-two addition is carried out for all the obtained codes so as to obtain the final code of the ith path of output. The calculating speed of channel codes can be greatly increased by the method so that integral business processing capacity is enhanced.

Description

A Fast Calculation Method of Channel Coding in Mobile Communication

technical field

The invention relates to channel coding technology, in particular to a fast calculation method for channel coding in mobile communication.

Background technique

Convolutional code is a channel coding technology proposed by Elias in 1955. It has been widely used in communication systems. The newly developed 3GPP also uses it as the main channel coding technology. Specifically, convolutional coding is to encode k information bits into n bits, and the n-k parity elements of this group are not only related to the k information symbols of this group, but also related to the previous N-1 time input encoder , where N=n+1, it can be seen that there are Nn interrelated symbols in the encoding process. Since the error correction capability of the convolutional code increases with the increase of N, and the error rate decreases exponentially with the increase of N, N is called the constraint length.

Similarly, in the decoding process of convolutional codes, not only the decoding information is extracted from the code groups received at the current moment, but also relevant information is extracted from the code groups received at previous or subsequent times. It is precisely because convolutional codes make full use of the correlation between groups in the coding process, and, compared with block coding, k and n are relatively small, and it is relatively easy to achieve optimal and quasi-optimal decoding .

The entire encoding process of the convolutional code encoder can be regarded as the convolution of the input information sequence with another sequence determined by the shift register and the XOR connection mode. Generally, the convolutional code is recorded as (n, k, N), Its encoding efficiency is Rc=k/n. According to the difference in coding efficiency, convolutional codes include: 1/2 convolutional code, 1/3 convolutional code, etc., among which 1/2 and 1/3 are coding efficiency. Here, coding efficiency can also be referred to as code rate.

Generally, the generator polynomial of a convolutional code encoder is shown in formula (1):

G(D)＝A ₀ +A ₁ D+...+A _n-1 D ^n-1 +A _n D ⁿ (1)

Taking the 1/2 code rate as an example, the generator polynomial of the 1/2 convolutional code encoder is shown in formula (2) and formula (3):

G ₀ (D)＝1+D ² +D ³ +D ⁴ +D ⁸ (2)

G ₁ (D)＝1+D+D ² +D ³ +D ⁵ +D ⁷ +D ⁸ (3)

In 3GPP, the structure of a convolutional code encoder is shown in Figure 1, wherein Figure 1a shows a 1/2 convolutional code encoder, and Figure 1b shows a 1/3 convolutional code encoder. As shown in Figure 1, the 3GPP convolutional code encoder includes eight shift registers. After an input sequence is processed differently by eight shift registers, it outputs two or three sequences. The specific number of output sequences is the same as the Depending on the code rate used. It can be seen from FIG. 1 that each output bit is the result of XOR of the current input bit and some previously input bits.

In fact, the conventional method of convolutional code encoding is to perform bit-by-bit operations according to the logic structure determined by the generator polynomial. Due to the difference of generating polynomials, the amount of operation is also different. In Fig. 1, there are 5 or 7 XOR instructions used to process each bit, so the amount of calculation is quite large, and it is not suitable for high-speed data communication.

At present, there are two typical calculation methods for convolutional code encoding: calculation based on generator polynomial state items and calculation based on impulse response. Among them, the main process of the method based on generator polynomial state item calculation is as follows: first, the bit stream to be encoded is divided into one or more processing units, and the processing unit is preferably consistent with the processing bit width of the processor. The processing bit width of the processor is generally 8, 16, 32 and so on. Then, the bit sequence corresponding to each state item is stored for later calculation and use. Here, the state item refers to each index item of D in the generator polynomial. For formula (2) and formula (3), the state item includes: 1, D, D ² , D ³ , D ⁴ , D ⁵ , D ⁷ , D ⁸ . Among them, the state item 1 corresponds to the current processing unit; the bit sequence corresponding to the state item D is 1 moment later than the current processing unit; the bit sequence corresponding to the state item D ² is 2 moments later than the current processing unit, and so on. Finally, according to the generator polynomial, the bit sequence corresponding to each state item is XORed to obtain the coding sequence of the current processing unit. Although the calculation speed of this method can reach lcycle/bit at the fastest, its calculation speed is limited by the processing bit width of the processor, only if the processor bit width is greater than or equal to twice the constraint length, that is, W≥2(N-1) Only then can each status item be obtained conveniently and quickly, otherwise the speed will be greatly reduced. Moreover, the coded data generated by this method is stored according to branches, and additional processor overhead is required when branches are merged.

For the calculation of convolutional code encoding based on impulse response, as shown in Figure 1, since the input bit at any time t will generate an impulse to the encoder, this impulse will affect time t and later t+1 until At time t+8, each time corresponds to an output bit, from c0 to c8. Then, just consider the input bit stream as individual impulses, and the corresponding output bit stream is the superposition of the individual impulse responses. And because the output bits corresponding to the impulse response of "0" are all 0, it can be ignored, and only the impulse response of "1" is considered. Therefore, the method based on the calculation of the impulse response consists of the following steps:

1) According to the data length of the encoder state, select an appropriate register and initialize it. For example: the encoder constraint length shown in Figure 1b is 9, and the data length is (9-1)/(1/3)=24, so three 32-bit registers are selected to store respectively: the impulse response accumulation result S, " 1” impulse response A, encoder output C.

2) Calculate the impulse response of "1" and store it in the register corresponding to A.

3) Iterate as follows:

a. Take an input bit, judge whether the input bit is 0 or 1, if it is 1, then execute step b, otherwise execute step c;

b. Accumulate the bit stream of register A into register S;

c. Shift the bit stream in the register S to the left by three bits and input it to the register C. The three bits are the encoded value of the input bit, and the result after the register S is shifted to the left by three bits is still retained in the register S;

d. Finally, output the encoded value in register C and return to step a.

The calculation method based on the impulse response, although the calculation speed is lcycle/bit level, is suitable for high-speed data communication, but this method is always a serial method, because there is a judgment process for each input bit, A block of data cannot be processed in parallel, so the improvement in computing speed is still limited.

Contents of the invention

In view of this, the main purpose of the present invention is to provide a fast calculation method for channel coding in mobile communication, which can greatly increase the calculation speed of channel coding, and further improve the overall service processing capability.

In order to achieve the above object, technical solution of the present invention is achieved in that way:

A fast calculation method for channel coding in mobile communication, the method comprises the following steps:

a. According to the logical structure of the currently used channel code encoder, obtain the relationship between each output of the channel code encoder and the initial state of each shift register in the encoder and the relationship between each input bit;

b. Store each function representation part of each output obtained separately, and use the different values of the independent variables contained in each storage part as address indexes to generate a lookup table corresponding to each storage part, the lookup The table includes the corresponding relationship between different values of the independent variable and each output;

c. When calculating the code, first obtain the respective codes according to the respective look-up tables for all the functions that represent the current calculation and the i-th channel output of the channel code encoder, and then add all the obtained codes modulo 2 to obtain the first The final encoding of the i output.

Wherein, step a further includes: simultaneously obtaining the relationship between the update state of each shift register in the currently used channel code encoder, the initial state of each shift register in the encoder, and each input bit.

In the above scheme, between step b and step c further includes: judging whether each storage part needs to be further subdivided, if necessary, further dividing the current storage part into more than one sub-storage part according to given conditions, and dividing After each sub-storage part generates a corresponding lookup table; otherwise, directly execute step c. Correspondingly, the method further includes: pre-setting the conditions that need to be subdivided, and then judging whether subdivision is required is judging whether the subdivision condition is met, and if so, subdivision is required; otherwise, no subdivision is required. Wherein, the condition for subdividing is: the storage capacity of the respective storage parts in step b is greater than a given storage capacity.

In the above scheme, if the current storage part is further divided into more than one sub-storage part, then step c is: represent all the functions currently calculated and output by the i-th channel of the channel code encoder according to the look-up tables corresponding to the respective sub-storage parts The respective codes are obtained, and then all obtained codes corresponding to each sub-storage part are added modulo 2 to obtain the code output by the i-th channel.

In the above scheme, the content of each storage part can be stored in a table respectively. In addition, the channel code encoder is: a code rate 1/2 convolutional code encoder, or a code rate 1/3 convolutional code encoder, or a Turbo code encoder.

In the fast calculation method of channel coding in mobile communication provided by the present invention, according to the logical structure corresponding to the current channel code encoder, the processing status of each input bit of the current channel code encoder is pre-acquired. The relationship between the initial state of each shift register and each input bit, and generate a corresponding lookup table according to the relationship; when performing corresponding channel coding, directly use the pre-generated lookup table to obtain the channel code encoder Each output in the current state, which can greatly improve the calculation speed of channel coding. Since the present invention is realized based on parallel processing, it has a high degree of parallelism, flexible processing, and is not limited by the processing bit width of the processor; moreover, it does not require any combination operation at one time, so it will not bring additional s expenses.

Description of drawings

Figure 1a is a schematic diagram of the logical structure of a 1/2 convolutional code encoder in 3GPP;

Figure 1b is a schematic diagram of the logical structure of a 1/3 convolutional code encoder in 3GPP;

Fig. 2 is the structural composition figure of universal channel code encoder;

Fig. 3 is a flow chart of the implementation of the method of the present invention.

Detailed ways

The basic idea of the present invention is: according to the logical structure corresponding to the current channel code encoder, the initial state of each output of the current channel code encoder and each shift register in the encoder is obtained in advance under different input bit processing states and the relationship between each input bit, and the relationship between the update state of each shift register in the encoder and the initial state of each shift register in the encoder and each input bit, and according to the relationship Corresponding look-up tables are generated respectively; when performing corresponding channel coding, the pre-generated look-up tables are directly used to obtain each output of the channel code encoder or the update status of the shift register in the current state.

As shown in Figure 2, Figure 2 is a general channel code encoder logic structure, the encoder has a total of N-way input and L-way output, assuming that the state of the encoder consists of R ₁ , R ₂ ,..., R _k represents, and the initial state of R _k ~ R ₁ is C _k ~ C ₁ . Of course, the encoder may also have no state. For example, the encoder is only composed of a modulo 2 plus circuit, that is, the output of the encoder is only related to the input at that time. In this case, only R _k ~ R ₁ ( C _k ~ C ₁ ) are removed. Suppose a byte input by INPUT ₁ is M ₁ =M _1,8 , M _1,7 , M _1,6 , M _1,5 , M _1,4 , M _1,3 , M _1,2 , M _{1, 1} , where M _{1, 8} is the most significant bit (MSB), M _{1, 1} is the least significant bit (LSB); a byte input from INPUT ₂ is M ₂ = M 2 _{, 8} , M _{2, 7} , M _{2, 6} , M _{2, 5} , M 2, 4, M _{2, 3} , M ₂ , 2, M _{2, 1} , where M _{2, 8} is MSB, M _{2, 1} is LSB; and so on, from INPUT One byte input is M _n = M _{n, 8} , M _{n, 7} , M _{n, 6} , M _{n, 5} , M _{n, 4} , M _{n, 3} , M _{n, 2} , M _{n, 1} , where M _{n, 8} is MSB, M _{n, 1} is LSB. Assume that after the encoder finishes encoding all input bits M _{n, i} (1≤n≤N, 1≤i≤8), the output bits are recorded as OUT ₁ , OUT ₂ , ..., OUT _L in sequence . Then, the expressions of the L-channel outputs of the transformed encoder and the encoder update states R ₁ ~ R _k are shown in Table 1 and Table 2, where Table 1 is the expression of the L-channel output of the general convolutional code encoder, and Table 1 The second is the expression of the update state of the general convolutional code encoder.

OUT₁＝φ₁(C₁, C₂,...., C_k)+f_{1, 1}(M_{1, 1}, M_{1, 2},...M_{1 ,8})+...+f_1,N(M_N,1,M_N,2... , M_{N, 8}) OUT₂＝φ₂(C₁, C₂,...., C_k)+f_{2, 1}(M_{1, 1}, M_{1, 2},...M_{1 ,8})+...+f_2,N(M_N,1,M_N,2... , M_{N, 8}) OUT₃＝φ₃(C₁, C₂,...., C_k)+f_3,1(M_1,1,M_1,2,...M_{1 ,8})+...+f_3,N(M_N,1,M_N,2... , M_{N, 8})  … OUT_L＝φ_L(C₁, C₂,...., C_k)+f_L,1(M_1,1,M_1,2,...M_{1 ,8})+...+f_L,N(M_N,1,M_N,2... , M_{N, 8})

Table I

In Table 1, φ _i (C ₁ , C ₂ , ..., C _k ) represents a function of C ₁ , ..., C _k , C ₁ to C _k are the initial states of the shift register, φ The subscript i of _i means the function output by the i-th road; f _1,1 (M _1,1 , M _1,2 ,...M _1,8 ) means M _1,1 , M _1,2 ,. ..M _{1, 8} functions, where M _{1, 2} represents the input, specifically, the second bit in a byte of the first input, and so on. The first 1 in the f _1,1 subscript indicates the first output, and the second 1 indicates the first input; "+" indicates modulo 2 addition.

R₁＝g₁(C₁, C₂, ..., C_k)+h_{1, 1}(M_{1, 1}, M_{1, 2},...M_{1 ,8})+...+h_1,N(M_N,1,M_N,2... , M_{N, 8}) R₂＝g₂(C₁, C₂, ..., C_k)+h_2,1(M_1,1,M_1,2,...M_{1 ,8})+...+h_2,N(M_N,1,M_N,2... , M_{N, 8}) R₃＝g₃(C₁, C₂, ..., C_k)+h_3,1(M_1,1,M_1,2,...M_{1 ,8})+...+h_3,N(M_N,1,M_N,2... , M_{N, 8})  … R_k＝g_k(C₁, C₂, ..., C_k)+h_k,1(M_1,1,M_1,2,...M_{1 , 8})+...+h_{k, N}(M_{N, 1}, M_{N, 2}... , M_{N, 8})

Table II

Similarly, in Table 2, g _i (C ₁ , C ₂ , ..., C _k ) represents a function of C ₁ , ..., C _k , and C ₁ to C _k are the initial State, the subscript i of g _i means it is the function of the i-th output; h _{1, 1} (M _{1, 1} M _{1, 2} ,...M _{1, 8} ) means it is M _{1, 1} , M _{1, 2} ,... M _{1, 8} functions, where M _{1, 2} represents the input, specifically, the second bit in a byte of the first input, and so on. h _1, the first 1 in the subscript of 1 indicates the first output, and the second 1 indicates the first input; "+" indicates modulo 2 addition.

In fact, the specific processing process of the present invention to calculate channel coding, as shown in Figure 3, includes the following steps:

Step 301: According to the logical structure of the currently used channel code encoder, obtain the relationship between each output of the encoder and the initial state of each shift register in the encoder and each input bit, and at the same time obtain the relationship between each output of the encoder. The relationship between the update state of each shift register and the initial state of each shift register in the encoder and each input bit;

Step 302: Store each function representation part of each output obtained separately, for example: divide Table 1 into N+1 sub-tables, as shown in Table 3, Table 4, and Table 5;

OUT₁＝φ₁(C₁, C₂,...., C_k) OUT₂＝φ₂(C₁, C₂,...., C_k) OUT₃＝φ₃(C₁, C₂,...., C_k) ... OUT_L＝φ_L(C₁, C₂,...., C_k)

Table three

OUT₁＝f_{1, 1}(M_{1, 1}, M_{1, 2},...M _{1, 8}) OUT₂＝f_{2, 1}(M_{1, 1}, M_{1, 2},...M _{1, 8}) OUT₃＝f_{3, 1}(M_{1, 1}, M_{1, 2},...M _{1, 8}) ... OUT_L＝f_{L, 1}(M_{1, 1}, M_{1, 2},...M _{1, 8})

Table four

OUT₁=f_{1, N}(M_{N, 1}, M_{N, 2}..., M _{N, 8}) OUT₂=f_{2, N}(M_{N, 1}, M_{N, 2}..., M _{N, 8}) OUT₃=f_{3, N}(M_{N, 1}, M_{N, 2}..., M _{N, 8}) ... OUT_L＝f_{L, N}(M_{N, 1}, M_{N, 2}..., M _{N, 8})

Table five

Step 303: generate a lookup table corresponding to each storage part, that is, generate a lookup table of N+1 sub-tables respectively;

Step 304: When calculating the code, firstly obtain the codes of all the functions representing the output of the i-th path currently calculated according to their corresponding look-up tables, and then add all the obtained codes modulo 2 to obtain the output of the road The final encoding requested.

A judgment can also be added between step 302 and step 303 to judge whether the parts stored separately need to be further subdivided, and if necessary, the current storage part is further divided into more than one sub-storage parts according to given conditions, and Each divided sub-storage part generates a corresponding look-up table respectively. Subdivision conditions can be set in advance, for example: if the storage capacity of the lookup table is greater than a certain value, it will be subdivided. Then, when subdividing, it will be determined how to subdivide according to the given value of the storage capacity. Specifically, the current storage part The storage capacity of the lookup table is 64K, and the given value is 32K, then the current storage part will be further divided into two storage parts. If subdivision is performed, then in step 304, the independent variable contained in each sub-storage part is used as the address index to search the corresponding look-up table, and then XOR all the search results.

For the storage mentioned in each of the above steps, a table can be set for storage. If two tables are divided from a certain table, these two tables can be called sub-tables of the original table.

Embodiment: Take the 1/2 code rate convolutional code encoding shown in FIG. 1a as an example.

According to the 3GPP standard, the 3GPP 1/2 code rate convolution code encoder has one output Input, two outputs Output0 and Output1, and the encoder uses eight shift registers. The specific logic structure is shown in Figure 1a. In this embodiment, each function representation part of each output is specifically represented by the corresponding initial state of the shift register and input bits.

The shift registers used to set the encoder shown in Figure 1a are recorded from left to right as: D8, D7, D6, D5, D4, D3, D2, D1; the initial state of each shift register is respectively recorded as: C8, C7, C6, C5, C4, C3, C2, C1; an input byte is recorded as M=M8M7M6M5M4M3M2M1, where M8 is MSB and M1 is LSB. Moreover, when M1 bits are input, the output Output0 of the encoder is recorded as OUT1, and Output1 is recorded as OUT2; when M2 bits are input, the output Output0 of the encoder is recorded as OUT3, and Output1 is recorded as OUT4; and so on, input M3, ......, M8 bits, the output Output0 and Output1 of the encoder are recorded as: OUT5, OUT6, OUT7, OUT8, OUT9, OUT10, OUT11, OUT12, OUT13, OUT14, OUT15, OUT16. Then the process of calculating 1/2 convolutional code encoding is:

Step 1 : According to the logical structure shown in Figure 1a, the relationship between the current update state of the shift register, the initial state of the shift register, and the input bit can be obtained when a bit is input, as shown in Table 6. For example: the shift register D1 is equal to C1 when no bit is input; it is equal to C2 after the first bit is input; it is equal to C3 after the second bit is input; and so on.

CLK INPUT D8 D7 D6 D5 D4 D3 D2 D1 0 C8 C7 C6 C5 C4 C3 C2 C1 1 M1 M1 C8 C7 C6 C5 C4 C3 C2 2 M2 M2 M1 C8 C7 C6 C5 C4 C3 3 M3 M3 M2 M1 C8 C7 C6 C5 C4 4 M4 M4 M3 M2 M1 C8 C7 C6 C5 5 M5 M5 M4 M3 M2 M1 C8 C7 C6 6 M6 M6 M5 M4 M3 M2 M1 C8 C7 7 M7 M7 M6 M5 M4 M3 M2 M1 C8 8 M8 M8 M7 M6 M5 M4 M3 M2 M1

Table six

At the same time, according to the logical structure shown in Figure 1a, the relationship between the output of the 1/2 convolutional code encoder, the initial state of the shift register, and the input bit can be obtained when a bit is input, as shown in Table 7. For example: after inputting the first bit, the first output of the 1/2 convolutional code encoder is M1+C7+C6+C5+C1; the second output is M1+C8+C7+C6+C4+C2+ C1, and so on. Wherein, "+" in the table means modulo 2 addition, and "+" in the following tables all means modulo 2 addition.

OUT1＝M1+C7+C6+C5+C1 OUT2＝M1+C8+C7+C6+C4+C2+C1 OUT3＝M2+C8+C7+C6+C2 OUT4＝M2+M1+C8+C7+C5+C3+C2 OUT5＝M3+M1+C8+C7+C3

OUT6＝M3+M2+M1+C8+C6+C4+C3 OUT7＝M4+M2+M1+C8+C4 OUT8＝M4+M3+M2+M1+C7+C5+C4 OUT9＝M5+M3+M2+M1+C5 OUT10＝M5+M4+M3+M2+C8+C6+C5 OUT11＝M6+M4+M3+M2+C6 OUT12＝M6+M5+M4+M3+M1+C7+C6 OUT13＝M7+M5+M4+M3+C7 OUT14＝M7+M6+M5+M4+M2+C8+C7 OUT15＝M8+M6+M5+M4+C8 OUT16＝M8+M7+M6+M5+M3+M1+C8

Table Seven

It is obviously inappropriate to directly generate the lookup table corresponding to Table 7, because there are sixteen independent variables M8～M1, C8～C1 in the table, correspondingly, there will be 2 ¹⁶ =65536 (64K) combinations, so that The storage capacity of the lookup table is too large, therefore, proceed to the second step.

The second step : store the part related to the input bit and the initial state of the shift register obtained, representing each output, respectively, that is: divide table 7 into two sub-tables, table 8 and table 9, wherein table 8 For each output and the representation part related to the input bit, Table 9 is the representation part for each output and the initial state of the shift register.

OUT1＝M1 OUT2＝M1 OUT3＝M2 OUT4＝M2+M1 OUT5＝M3+M1 OUT6＝M3+M2+M1 OUT7＝M4+M2+M1 OUT8＝M4+M3+M2+M1 OUT9＝M5+M3+M2+M1

OUT10＝M5+M4+M3+M2 OUT11＝M6+M4+M3+M2 OUT12＝M6+M5+M4+M3+M1 OUT13＝M7+M5+M4+M3 OUT14＝M7+M6+M5+M4+M2 OUT15＝M8+M6+M5+M4 OUT16＝M8+M7+M6+M5+M3+M1

table eight

OUT1＝C7+C6+C5+C1 OUT2＝C8+C7+C6+C4+C2+C1 OUT3＝C8+C7+C6+C2 OUT4＝C8+C7+C5+C3+C2 OUT5＝C8+C7+C3 OUT6＝C8+C6+C4+C3 OUT7＝C8+C4 OUT8＝C7+C5+C4 OUT9＝C5 OUT10＝C8+C6+C5 OUT11＝C6 OUT12＝C7+C6 OUT13＝C7 OUT14＝C8+C7 OUT15＝C8 OUT16＝C8

Table nine

Step 3 : Using the independent variables in Table 8 or Table 9 as address indexes respectively, generate a lookup table corresponding to the storage part of Table 8 or Table 9.

Here, taking Table 8 as an example, the specific process of generating the lookup table is: first list 256 values of M1~M8; Each output value corresponding to different values; with M1-M8 as the address index, all output values are stored in the register; the final 256 values for each output are the required lookup table. For example: when the values of M1-M8 are 01111010, since OUT5 is M3+M1, where M3=1 and M1=0, the calculated value of OUT5 is 1, and the calculation methods for other outputs are the same.

Step 4 : When actually performing convolutional encoding, address the two lookup tables respectively, and then add the two obtained values modulo 2 to obtain the final encoded value. That is to say, the corresponding two OUTn values are respectively obtained according to the two lookup tables, and then the two OUTn values are added modulo 2, and the obtained result is the final OUTn output.

Since the lookup tables are generated for Table 8 and Table 9 respectively, the required storage space is 2 ⁸ ×2=512 words, and compared to 2 ¹⁶ , the storage capacity is reduced to 1/128 of the original.

The calculation method for the 1/3 code rate convolutional code encoding shown in Figure 1b is exactly the same as the above-mentioned embodiment, except that the 1/3 code rate convolutional code encoder has three outputs, correspondingly, there will be 24 OUTs. For other channel codes, as long as they can be calculated by determining the logical structure, the method of the present invention can be used, such as Turbo code, etc., and the specific basic implementation process is also the same as the above-mentioned embodiment.

Compared with single-bit calculation, the method of the invention can save time and space. For example: if the environment has very strict space requirements, 16 bits can be divided into two 8 bits, and the space can be saved as the original 2 ^-7 = 1/128; 8 bits can also be divided into two 4 bits, and the space can be saved as the original At the same time, it can also save the cumbersome process of stitching two or three bits into a word or byte, and of course saves operation time.

The method of the present invention is also applicable to a single bit, that is, a bit that does not form a byte, and only needs to remove the first few bits of the code obtained by addressing. In addition, the output bit stream of the method of the present invention is the combined output of the output bit streams of each branch, and no separate combining operation is required.

For the amount of calculation of the inventive method, it can be specifically calculated, such as: the input code stream is a group of every 8 bits, then the calculation amount of the convolutional code encoder with a code rate of 1/2 and a constraint length of 9 is, two One table lookup operation and one XOR operation; when the code rate is 1/3, it is only necessary to change the storage method of the table from word storage to double word storage, no additional overhead is required, just increase the storage capacity . In addition, with the method of the present invention, for the convolutional code encoder shown in FIG. 1 , its calculation speed can reach a speed lower than lcycle/bit.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.

Claims (8)

1. the quick calculation method of chnnel coding in the mobile communication is characterized in that this method may further comprise the steps:

A. according to the logical construction of currently used channel code encoder, obtain the initial condition of each shift register in every road output of this channel code encoder and the encoder and the relation between the input bit of every road;

Each function representation part storage respectively of b. the every road that is obtained being exported, and the different values of the independent variable that comprises with each storage area are allocation index, generate the look-up table of each storage area correspondence respectively, comprise the different values of described independent variable and the corresponding relation between the output of every road in the described look-up table;

C. when calculation code, will represent that earlier all functions current calculating, the output of channel code encoder i road respectively according to each self-corresponding look-up table acquisition coding separately, carry out all codings that obtained mould 2 again and add the final coding that obtains the output of i road.

2. method according to claim 1, it is characterized in that step a also comprises: obtain the initial condition of each shift register in the update mode of each shift register in the currently used channel code encoder and the encoder and the relation between the input bit of every road simultaneously.

3. method according to claim 1, it is characterized in that, further comprise between step b and the step c: judge whether each storage area needs to continue segmentation, if desired, then current storage area further is divided into sub-storage area more than, and each the sub-storage area after dividing is generated corresponding look-up table respectively by specified criteria; Otherwise, direct execution in step c.

4. method according to claim 3 is characterized in that, this method further comprises: set in advance the condition that need segment, then described judge whether to be subdivided into judge whether to meet sub-divided condition, if meet, then need the segmentation; Otherwise do not need segmentation.

5. method according to claim 4 is characterized in that, the described condition of segmenting is: the memory space of the storage area of difference described in the step b is greater than given memory space.

6. method according to claim 3, it is characterized in that, if current storage area further is divided into sub-storage area more than, then step c is: will represent that all functions current calculating, channel code encoder i road output obtain separately coding according to the look-up table of sub-storage area correspondence separately respectively, and again the coding of each sub-storage area of correspondence of all acquisitions be carried out mould 2 and add the coding that obtains the output of i road.

7. method according to claim 1 is characterized in that, the content of each storage area is stored in the table respectively.

8. method according to claim 1 is characterized in that, described channel code encoder is: the encoder for convolution codes of the encoder for convolution codes of 1/2 code check or 1/3 code check or Turbo code encoder.

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