CN109698693A - Using two-sided integrated programmable gate array - Google Patents
Using two-sided integrated programmable gate array Download PDFInfo
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- CN109698693A CN109698693A CN201710980989.0A CN201710980989A CN109698693A CN 109698693 A CN109698693 A CN 109698693A CN 201710980989 A CN201710980989 A CN 201710980989A CN 109698693 A CN109698693 A CN 109698693A
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- programmable gate
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- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000003860 storage Methods 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 abstract description 3
- 238000004364 calculation method Methods 0.000 description 6
- 241000193935 Araneus diadematus Species 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007711 solidification Methods 0.000 description 2
- 230000008023 solidification Effects 0.000 description 2
- 244000089409 Erythrina poeppigiana Species 0.000 description 1
- 235000009776 Rathbunia alamosensis Nutrition 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003455 independent Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/1776—Structural details of configuration resources for memories
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- Mathematical Physics (AREA)
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- Computer Hardware Design (AREA)
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- Computer Networks & Wireless Communication (AREA)
- Logic Circuits (AREA)
Abstract
The present invention proposes a kind of using two-sided integrated programmable gate array, it is a single (monolithic) chip and contains multiple programmable computing units, multiple programmable logic chips and multiple reconfigurable interconnections, and each programmable computing unit contains the writeable storage array of one basic function look-up table (LUT) of a storage.Programmable computing unit and programmable logic cells are respectively formed at the different surfaces (front and back) of same semi-conductive substrate, and are electrically coupled by penetrating substrate connection.
Description
Technical field
The present invention relates to integrated circuit fields, more precisely, being related to programmable gate array.
Background technique
Programmable gate array belongs to semicustom integrated circuit, i.e., by backend process or field programming, realizes to logic electricity
The customization on road.United States Patent (USP) 4,870,302 discloses a kind of programmable gate array.It contains multiple programmable logic cells
(configurable logic element or configurable logic block) and reconfigurable interconnection
(configurable interconnect or programmable interconnect).Wherein, programmable logic cells exist
Realize displacement, logic NOT, AND(logical AND to the property of can choose under setting signal control), OR(logic sum), NOR(and non-),
NAND(and non-), XOR(exclusive or) ,+(arithmetic adds) ,-functions such as (arithmetic subtracts)；Reconfigurable interconnection can be under setting signal control
Selectively realize the functions such as connection, the disconnection between two interconnection lines.
Currently, many applications all refer to the calculating of complicated function.Complicated function typically contains multiple independents variable, it is basic
A kind of combination of function.Basic function contains one or a small number of independent variable, and example includes surmounting function, such as index (exp), right
Number (log), trigonometric function (sina, cos) etc..In order to guarantee to execute speed, performance application requirement realizes complexity with hardware
Function.In existing programmable gate array, complicated function to solidify computing unit by realizing.These solidifications calculate single
Member is a part of stone (hard block), and circuit has been cured, cannot reconfigure to it.It is obvious that solidification meter
Further applying for programmable gate array will be limited by calculating unit.In order to overcome this difficulty, the present invention is by programmable gate circuit
Concept makes to solidify computing unit programmable.Particularly, programmable gate circuit in addition to containing programmable logic cells with
Outside, also containing programmable computing unit.Realize any one of many kinds of function to the programmable computing unit property of can choose.
Summary of the invention
The main object of the present invention is to promote programmable gate circuit in the application in complicated calculations field.
It is a further object of the present invention to provide a kind of programmable gate circuits, and not only its logic function can be customized, meter
Calculating function can also be customized.
A kind of it is a further object of the present invention to provide computing capabilitys more flexible, more powerful programmable gate array.
A kind of it is a further object of the present invention to provide chip areas smaller, the lower programmable gate array of cost.
In order to realize that these and other purpose, the present invention propose a kind of programmable gate array.It is a single
(monolithic) chip and contain multiple programmable computing units and multiple programmable logic cells, they are respectively formed at together
The front and back sides of semi-conductive substrate.The programmable gate array also contains multiple reconfigurable interconnections, these reconfigurable interconnections are distributed in
With the front and back sides of semi-conductive substrate.
Each programmable computing unit contains at least one writeable storage array, which stores a kind of basic
The look-up table (LUT) of function.It may be programmed the use of computing unit in two stages: setup phase and calculation stages.In setting rank
Section needs for the LUT of required function to be loaded into writeable storage array according to user；In calculation stages, obtained by searching for LUT
Obtain the value of the function.Due to using writeable storage array, different functions may be implemented with a batch of chip.And
And the programmable gate array for being based on multiple program storage (MTP) array, due to that can add to MTP array in different periods
The LUT of different functions is carried, which is able to achieve Reconfigurable Computation.
Each programmable logic cells selectively realize a kind of logical operation from a logical operation library.In addition, can compile
Realize one of a variety of connections to the journey connection property of can choose.During the realization of complicated function, complicated function first by
It is decomposed into multiple basic functions.Then corresponding programmable computing unit is set for each basic function, achieves corresponding
Basic function.Finally, realizing required complicated function by setting programmable logic cells and reconfigurable interconnection.
Correspondingly, the present invention proposes a kind of programmable gate array (400), it is characterised in that contains: one containing there are two surfaces
Semiconductor substrate (0), which includes one positive (0F) and a reverse side (0B)；Multiple programmable computing units (100,
100AA-100AD), which contains at least one writeable storage array (110), the writeable storage array
(110) at least partly look-up table (LUT) of a basic function is stored；Multiple programmable logic cells (200,200AA-
200AD), which selectively realizes a kind of logical operation from a logical operation library；It is multiple should
Programmable computing unit (100AA-100AD) and the programmable logic cells (200AA-200AD) are selectively coupled to be may be programmed
It connects (300)；By to this may be programmed computing unit (100AA-100AD), the programmable logic cells (200AA-200AD) and
The reconfigurable interconnection (300) is programmed to realize a complicated function, which is a kind of combination of the basic function；
The programmable computing unit (100,100AA-100AD) and the programmable logic cells (200,200AA-200AD) point
It is not formed in the different surfaces of the semiconductor substrate (0), and is electrically coupled by multiple across substrate connection (160).
Detailed description of the invention
Fig. 1 is a kind of symbol of programmable computing unit.
Fig. 2 is a kind of substrate circuitry layout of programmable computing unit.
Fig. 3 is a kind of layout of programmable gate array.
Fig. 4 indicates a kind of two service life of restructural gate array.
Fig. 5 A discloses a kind of link library that reconfigurable interconnection is realized；Fig. 5 B discloses a kind of patrolling for programmable logic cells realization
Collect operation library.
Fig. 6 is a kind of layout of this kind of programmable gate array specific implementation.
Fig. 7 A is a kind of front perspective view of programmable gate array chip；Fig. 7 B is the back side of the programmable gate array chip
Perspective view；Fig. 7 C is the sectional view of the programmable gate array chip.
It is noted that these attached drawings are only synoptic diagrams, their nots to scale (NTS) are drawn.For the sake of obvious and is convenient, in figure
Portion size and structure may zoom in or out.In different embodiments, identical symbol typicallys represent corresponding or similar
Structure.
Specific embodiment
Fig. 1 is a kind of symbol of programmable computing unit 100.Its input terminal IN includes input data 115, output end OUT
Including output data 135, it includes setting signal 125 that end CFG, which is arranged,.When setting signal 125 is " writing ", list is calculated programmable
The LUT of basic function needed for being written in member 100.When setting signal 125 is " reading ", read from programmable computing unit 100
Value in LUT.Fig. 2 is a kind of circuit arrangement map of programmable computing unit 100.In this embodiment, LUT is stored at least one
In a writeable storage array 110.The circuit further includes the peripheral circuit of writeable storage array 110: X-decoder 15 and Y-decoder
(including reading circuit) 17 etc..Writeable storage array 110 can be RAM or ROM.The example of RAM includes SRAM, DRAM etc.；ROM
Example include OTP(one-time programming), MTP(more times programming) etc..Wherein, MTP includes EPROM, EEPROM, flash memory, 3D-
NAND, 3D-XPoint etc..
Fig. 3 indicates a kind of programmable gate array 400.It contains regularly arranged programmable module 400A and programmable module
400B etc..Each programmable module (such as 400A), which is contained multiple programmable computing units (such as 100AA-100AD) and be may be programmed, patrols
It collects unit (such as 200AA-200AD).Programmable computing unit (such as 100AA-100AD) and programmable logic cells (such as
Contain programmable channel 320,340 between 200AA-200AD)；Between programmable module 400A and programmable module 400B,
Contain programmable channel 310,330,350.Programmable channel 310-350 contains multiple reconfigurable interconnections 300.For being familiar with ability
It, can also be using the design such as sea of gates (sea-of-gates) other than programmable channel for the professional person in domain.
Fig. 4 indicates two service life 620 and 660 of restructural gate array 400.It is two that first service life 620, which is divided to,
Stage: setup phase 610 and calculation stages 630.In setup phase 610, being needed according to user will be relevant to a basic function
Look-up table is loaded into MTP array 110；In calculation stages 630, corresponding LUT is searched in MTP array 110 to obtain the base
The value of this function.Similarly, the second service life 660 also contains identical setup phase 650 and calculation stages 670.It is restructural
Calculate be particularly suitable for SIMD(single-instruction multiple-data stream (SIMD)) data processing.Once LUT is loaded into MTP times in setup phase 610
After column 110, mass data can be sent into programmable computing unit 100 and handled, and obtain higher processing speed.
There are many example application of SIMD, as, to the same operation of multiple pixels or vector operation, used in scientific algorithm in image procossing
Extensive parallel computing etc..In addition, programmable gate array can also be may be programmed the pipelining of the calculating in computing unit,
To further increase throughput.
Fig. 5 A discloses a kind of link library that reconfigurable interconnection 300 is able to achieve.The reconfigurable interconnection 300 and United States Patent (USP) 4,
The reconfigurable interconnection disclosed in 870,302 is similar.It uses a kind of connection type of following link libraries: a) interconnection line 302/304
It is connected, interconnection line 306/308 is connected, but 302/304 is not attached to 306/308；B) interconnection line 302/304/306/308 is homogeneous
Even；C) interconnection line 306/308 is connected, and interconnection line 302,304 is not attached to, and is not also connected with 306/308；D) interconnection line 302/304
It is connected, interconnection line 306,306 is not attached to, and is not also connected with 302/304；E) interconnection line 302,304,306,306 is not attached to.?
In this specification, the symbol "/" between two interconnection lines indicates that two interconnection lines are connected, the symbol between two interconnection lines
", " indicate that two interconnection lines are not attached to.
Fig. 5 B discloses a kind of logical operation library that programmable logic cells 200 are able to achieve.It is input data that it, which inputs A and B,
210,220, output C are output data 230.What is disclosed in the programmable logic cells 200 and United States Patent (USP) 4,870,302 compiles
Journey logic unit is similar.It may be implemented at least one of following logical operation libraries: C=A, A logic NOT, A displacement, AND (A,
B), OR (A, B), NAND (A, B), NOR (A, B), XOR (A, B), arithmetic add A+B, arithmetic to subtract A-B etc..Programmable logic cells
200 can also be containing sequential circuit elements such as register, triggers, with the operation such as assembly line of practising.
Fig. 6 is a kind of specific implementation of programmable gate array 400, it is for realizing a complicated function: e=a.sin(b)+
c.cos(d).Reconfigurable interconnection 300 is using the representation in Fig. 5 A in programmable channel 310-350: there is dot in crosspoint
Reconfigurable interconnection indicate cross spider be connected, crosspoint without dot reconfigurable interconnection indicate cross spider be not attached to, disconnection can
Programming connection indicates that the interconnection line disconnected is divided into two mutual disjunct interconnection line segments.In this embodiment, it may be programmed and calculate
Unit 100AA is arranged to log (), and calculated result log (a) is sent to the first input of programmable logic cells 200AA.
Programmable computing unit 100AB is arranged to log [sin ()], and calculated result log [sin (b)] is sent to programmable logic
The second input of unit 200AA.Programmable logic cells 200AA is arranged to " arithmetic adds ", calculated result log (a)+log
[sin (b)] is sent to programmable computing unit 100BA.Programmable computing unit 100BA is arranged to exp (), calculates knot
Fruit exp { log (a)+log [sin (b)] }=a.Sin (b) is sent to the first input of programmable logic cells 200BA.Similarly,
By setting appropriate, computing unit 100AC, 100AD, programmable logic cells 200AC, programmable computing unit may be programmed
The result c of 100BC.Cos (d) is sent to the second input of programmable logic cells 200BA.Programmable logic cells 200BA quilt
It is set as " arithmetic adds ", a.Sin (b) and c.Cos (d) is added herein, and final result is sent to output e.It is obvious that being set by changing
It sets, programmable gate array 400 can also realize other complicated functions.
Fig. 7 A is a kind of front perspective view of programmable gate array chip 400；Fig. 7 B is the programmable gate array chip 400
Back perspective view；Fig. 7 C is the sectional view of the programmable gate array chip 400.The programmable gate array chip 400 is one single
Core (monolithic) chip simultaneously contains semi-conductive substrate 0.The substrate 0 contains the front direction 0F(+z) and the back side side 0B(-z
To).In this embodiment, programmable logic cells 200AA-200BB is formed in the positive 0F of substrate 0；Programmable computing unit
100AA-100BB is formed in the back side 0B of substrate 0, penetrates substrate connection (160, including 160a- by multiple between them
160c) it is electrically coupled.The example for penetrating substrate connection (160, including 160a-160c) includes penetrating silicon wafer channel (TSV).
In other embodiments, it may be programmed the positive 0F that computing unit 100AA-100BB is formed in substrate 0；Programmable logic cells
200AA-200BB is formed in the back side 0B of substrate 0.
It is this that programmable logic cells 200AA-200BB and programmable computing unit 100AA-100BB is being formed into substrate just
The integration mode on anti-two sides is referred to as two-sided integrated.Two-sided integrated can improve calculates density and computation complexity.Using traditional
Two dimension is integrated, and the area of programmable gate array is the sum of programmable logic cells and programmable computing unit.Using two-sided integrated
Afterwards, LUT moves on to other one side of substrate from side, and programmable gate array becomes smaller, and calculates density and reinforces.It can further, since constituting
The logic transistor of programmed logic unit 200AA-200BB and the storage crystal for constituting programmable computing unit 100AA-100BB
Pipe is respectively formed on the different surfaces of substrate, their manufacturing process can be separately optimized.
This specification is by taking field programmable gate array (FPGA) as an example.In FPGA, wafer will complete all process steps (including
All programmable computing unit, programmable logic cells and reconfigurable interconnection).It, can be by the way that programmable connect be arranged at programming scene
Fetch the function of defining FPGA.The example of above-mentioned FPGA can easily be generalized to traditional programmable gate array.In tradition
In programmable gate array, wafer is only semi-finished, i.e., wafer production is only completed programmable computing unit and programmable logic cells, but
Reconfigurable interconnection is not completed.After the function of chip determines, programmable channel 310-350 is customized by backend process.
It should be appreciated that under the premise of not far from the spirit and scope of the present invention, it can be to form and details of the invention
It is modified, this does not interfere them using spirit of the invention.Therefore, in addition to the spirit according to appended claims,
The present invention should not be any way limited.
Claims (10)
1. a kind of programmable gate array (400), it is characterised in that contain:
One containing there are two the semiconductor substrate (0) on surface, which includes one positive (0F) and a reverse side (0B)；
Multiple programmable computing units (100,100AA-100AD), programmable computing unit (100) are writeable containing at least one
Storage array (110), the writeable storage array (110) store at least partly look-up table (LUT) of a basic function；
Multiple programmable logic cells (200,200AA-200AD), the programmable logic cells (200) are from a logical operation library
In selectively realize a kind of logical operation；
It is multiple that this be may be programmed into computing unit (100AA-100AD) and the programmable logic cells (200AA-200AD) selectivity
The reconfigurable interconnection (300) of coupling；
By to this may be programmed computing unit (100AA-100AD), the programmable logic cells (200AA-200AD) and this can compile
Journey connection (300) is programmed to realize a complicated function, which is a kind of combination of the basic function；
The programmable computing unit (100,100AA-100AD) and the programmable logic cells (200,200AA-
It 200AD) is respectively formed at the different surfaces of the semiconductor substrate (0), and penetrates substrate connection (160) by multiple and be electrically coupled.
2. programmable gate array (400) according to claim 1, it is further characterized in that: at least partly described programmable company
It connects (300) and is located at positive (0F).
3. programmable gate array (400) according to claim 1, it is further characterized in that: at least partly described programmable company
It connects (300) and is located at the back side (0B).
4. programmable gate array (400) according to claim 1, it is further characterized in that: the writeable storage array (110) is
RAM。
5. programmable gate array (400) according to claim 1, it is further characterized in that: the writeable storage array (110) is
ROM。
6. programmable gate array (400) according to claim 5, it is further characterized in that: the ROM is one-time programming storage
Device (OTP).
7. programmable gate array (400) according to claim 5, it is further characterized in that: the ROM is multiple program storage
Device (MTP).
8. programmable gate array (400) according to claim 1, it is further characterized in that: should be across substrate connection (160)
Penetrate silicon wafer channel (TSV).
9. programmable gate array (400) according to claim 1, it is further characterized in that: its use process includes a setting
Stage (610) needs the LUT by a function to be loaded into writeable storage array (110) according to user at this stage.
10. programmable gate array (400) according to claim 1, it is further characterized in that: its use process includes a use
Stage (630) searches the LUT at this stage to obtain the value of the function.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710980989.0A CN109698693A (en) | 2017-10-20 | 2017-10-20 | Using two-sided integrated programmable gate array |
| US15/793,933 US10141939B2 (en) | 2016-03-05 | 2017-10-25 | Configurable computing array using two-sided integration |
| US16/059,023 US10312917B2 (en) | 2016-03-05 | 2018-08-08 | Configurable computing array for implementing complex math functions |
| US16/186,571 US10700686B2 (en) | 2016-03-05 | 2018-11-11 | Configurable computing array |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710980989.0A CN109698693A (en) | 2017-10-20 | 2017-10-20 | Using two-sided integrated programmable gate array |
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| CN109698693A true CN109698693A (en) | 2019-04-30 |
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| CN201710980989.0A Pending CN109698693A (en) | 2016-03-05 | 2017-10-20 | Using two-sided integrated programmable gate array |
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| CN109698692A (en) * | 2017-10-20 | 2019-04-30 | 成都海存艾匹科技有限公司 | Using two-sided integrated programmable gate array |
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| CN109698692A (en) * | 2017-10-20 | 2019-04-30 | 成都海存艾匹科技有限公司 | Using two-sided integrated programmable gate array |
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Application publication date: 20190430 |