CN109542817B - Universal electronic countermeasure equipment control framework - Google Patents
Universal electronic countermeasure equipment control framework Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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Abstract
The invention provides a control architecture of a universal electronic countermeasure device. The system comprises a DSP control board and a plurality of FPGA processing boards; a plurality of functional sub-modules, a co-processing CPU, an EMIF bus transceiver module and a RapidIO bus transceiver module are arranged in the FPGA processing chip; the DSP processing chip and the FPGA processing chip adopt a RapidIO bus and an EMIF bus to complete information interaction; the internal interconnection bus of the FPGA processing chip takes three main controls as command initiators, namely a RapidIO bus, an EMIF bus and a co-processing CPU; the FPGA processing board comprises a plurality of FPGA processing chips and a RapidIO switch; the FPGA processing chips are bridged by adopting an interconnection bus, and each FPGA processing chip is connected with a RapidIO switch inside the FPGA processing board; and the RapidIO switch in each FPGA processing board is connected with the RapidIO switch in the DSP control board through an optical fiber or a back board. The invention improves the universality and expandability of the electronic countermeasure control system and reduces the delay of control information.
Description
Technical Field
The invention belongs to the technical field of software radio, and particularly relates to a control framework of a universal electronic countermeasure device.
Background
In recent years, the fields of communication, radar, and electronic countermeasure have been rapidly developed. The demand for general low-delay and large-bandwidth data control and exchange gradually rises, and particularly for electronic countermeasure equipment with strict requirements on data processing delay and bandwidth, a large amount of high-precision data is often required to be acquired and processed in a short time, so that the control, exchange and processing of ultra-wideband data are required to be completed in real time. With the rapid development of the characteristics of the processing chip, such as the operating speed and the transmission bandwidth. A control framework based on combination of an FPGA and a DSP is a solution which can completely meet the current requirements. However, the existing FPGA and DSP have single interconnection structure and poor universality. The DSP is difficult to directly control each submodule inside the FPGA to complete real-time control and interaction of data, and all the submodules need to be bridged by special modules in the FPGA, so that the data control and processing time is prolonged, information in each module cannot be effectively interacted, and the expandability is poor. Different devices require respective dedicated control processing architectures, resulting in increased time cost and technical risk for development of the devices.
Disclosure of Invention
The invention provides a control framework of universal electronic countermeasure equipment, which is characterized in that on the basis of the original control framework, a method for processing bridging of a high-speed interconnection bus among chips and a high-speed bus inside the chip is adopted, and all modules work cooperatively through functional division, so that the universality and expandability of an electronic countermeasure control system are improved, the delay of control information is reduced, and the data transmission and processing capacity is improved.
In order to solve the technical problems, the invention provides a control framework of a universal electronic countermeasure device, which comprises a DSP control board and a plurality of FPGA processing boards, wherein the DSP control board comprises a DSP processing chip, an FPGA processing chip and a RapidIO switch; a plurality of functional sub-modules, a co-processing CPU, an EMIF bus transceiver module and a RapidIO bus transceiver module are arranged in the FPGA processing chip; the functional submodule, the coprocessing CPU, the EMIF bus transceiver module and the RapidIO bus transceiver module are all connected with an internal interconnection bus of the FPGA processing chip; the DSP processing chip and the FPGA processing chip adopt a RapidIO bus and an EMIF bus to complete information interaction; the internal interconnection bus of the FPGA processing chip takes three main controls as command initiators, namely a RapidIO bus, an EMIF bus and a co-processing CPU; the FPGA processing board comprises a plurality of FPGA processing chips and a RapidIO switch; each FPGA processing chip is internally provided with a plurality of functional sub-modules, a co-processing CPU and a RapidIO bus transceiver module; each functional submodule, the coprocessing CPU and the RapidIO bus transceiver module are all connected with an internal interconnection bus of the FPGA processing chip; the FPGA processing chips are bridged by adopting an interconnection bus, and each FPGA processing chip is connected with a RapidIO switch inside the FPGA processing board; and the RapidIO switch in each FPGA processing board is connected with the RapidIO switch in the DSP control board through an optical fiber or a back board.
Further, in the DSP control panel, a RapidIO bus is used for the interaction of bandwidth data between the FPGA processing chip and the DSP processing chip; the EMIF bus is used for controlling the receiving and sending of commands; and the co-processing CPU completes the control and initialization of the interior of the FPGA processing chip.
Furthermore, in the DSP control board, the three main controls are all bridged through a RapidIO bus and then directly control each functional submodule in the FPGA processing chip.
Further, the functional sub-modules are one or more of Aurora protocol, algorithm processing module, JESD204B protocol, UART module, memory controller and register control module; the Aurora protocol is used for controlling information interaction between FPGA processing chips; the JESD204B protocol is used for processing bandwidth data interaction between chips by the FPGA; the UART module is used for reading, writing and monitoring debugging information of the FPGA processing chip; the storage controller is used for controlling the external storage device to finish the storage of data and the loading of initialization data; the register control module is used for finishing the control and monitoring of the algorithm processing module.
Further, after the electronic countermeasure equipment is powered on, the DSP processing chip firstly completes self initialization, configures each RapidIO switch in the electronic countermeasure equipment and determines the node ID of each networking FPGA processing chip; after confirming that the configuration state of each node is normal, initializing an internal interconnection bus of each FPGA processing chip, and completing address mapping of each functional sub-module in each FPGA processing chip; the DSP processing chip sends an initialization command to the co-processing CPU in each FPGA processing chip in an interrupt mode, the co-processing CPU reports the self-checking state of each functional submodule in the FPGA processing chip after finishing work, if the self-checking state is normal, the DSP processing chip enters a normal working state, and otherwise, a fault code is reported.
Furthermore, the internal control flow of the FPGA is initiated by the co-processing CPU, after the co-processing CPU receives an initialization command sent by the DSP processing chip, the co-processing CPU firstly releases the reset of each functional sub-module, sequentially controls each functional sub-module to complete self-checking, reads a self-checking state register of each functional sub-module, and finally gathers the self-checking state and feeds back the self-checking state to the DSP processing chip; after self-checking is completed, loading initialization parameters required by FPGA work from an external storage device, and configuring a register required by algorithm work; after the FPGA processing chip starts to work normally, the co-processing CPU enters a monitoring state, monitors the working state of each functional sub-module component and waits for the next working instruction of the DSP processing chip.
Compared with the prior art, the invention has the remarkable advantages that: the invention is a general expandable electronic countermeasure equipment control framework based on FPGA (field programmable gate array) and DSP (digital signal processor), aiming at the defects of slow processing speed, high delay, low data transmission processing capability, poor expandable capability and the like of the control framework in the electronic countermeasure equipment, the invention provides a brand-new general expandable solution with low delay and large bandwidth data exchange capability; the electronic countermeasure equipment completes the interconnection of the FPGA and the DSP through a RapidIO high-speed bus; the interior of the FPGA is connected with each module by adopting a high-speed low-delay interconnection bus, a soft CPU (central processing unit) is realized in the FPGA to be used as a coprocessor of a DSP, and a system integrating functions of data transmission, control, processing, storage and the like is constructed; any module in the FPGA in the transparent control system can be directly controlled and data communication can be completed through the bridge DSP among the interconnection buses.
Drawings
FIG. 1 is a basic block diagram of the architecture of the present invention;
FIG. 2 is a schematic diagram of the internal control architecture of the DSP control board according to the present invention;
FIG. 3 is a schematic diagram of the internal control architecture of the FPGA processing board of the present invention;
FIG. 4 is a control workflow of the electronic countermeasure apparatus according to the present invention;
FIG. 5 is a flow of work within the FPGA of the present invention.
Detailed Description
It is easily understood that various embodiments of the present invention can be conceived by those skilled in the art according to the technical solution of the present invention without changing the essential spirit of the present invention. Therefore, the following detailed description and the accompanying drawings are merely illustrative of the technical aspects of the present invention, and should not be construed as all of the present invention or as limitations or limitations on the technical aspects of the present invention.
The invention is based on the high-speed interconnection bus technology, adopts a control framework combining the FPGA and the DSP, and completes real-time data interaction and control between boards and in chips through the RapidIO high-speed bus between the chips and the FPGA standard interconnection bus. Through the direct connection between the backboard of the board card and the optical fiber, the number of the FPGA processing boards can be expanded. The DSP can complete the control of any component in the architecture in real time to realize the system function. The basic framework of the architecture is shown in fig. 1.
The control framework of the universal electronic countermeasure equipment comprises a DSP control board and a plurality of FPGA processing boards.
As shown in fig. 2, the DSP control board includes a DSP processing chip, an FPGA processing chip, and a RapidIO switch. The FPGA processing chip internally comprises a plurality of functional sub-modules, a soft CPU, an EMIF bus transceiving module and a RapidIO bus transceiving module. The functional sub-modules are, for example, Aurora protocol, algorithm processing module, JESD204B protocol, UART module, memory controller, register control module, and the like. The functional sub-module and the soft CPU are mounted on an internal interconnection bus of the FPGA processing chip. The DSP control panel is responsible for the control and external interface of the whole electronic countermeasure equipment. The DSP control board adopts gigabit Ethernet to communicate with external master control equipment. And in the DSP control panel, a RapidIO bus and an EMIF bus are adopted between the DSP processing chip and the FPGA processing chip to complete information interaction. The internal interconnection bus of the FPGA processing chip takes three main controls as a command initiator: a RapidIO bus, an EMIF bus and an FPGA internal co-processing CPU. The RapidIO bus is mainly used for interaction of large-bandwidth data between the FPGA processing chip and the DSP processing chip, such as DMA operation, algorithm processing result reading and the like; the EMIF bus mainly receives and transmits control commands with higher delay requirement and lower data volume, and the transmission pressure of the RapidIO bus is relieved; and the FPGA internal co-processing CPU completes the control and initialization of the FPGA. The three main controls can directly control each sub-module connected with the interconnection bus in the FPGA chip. The Aurora protocol is used for exchanging control information among the FPGAs; the JESD204B protocol is used for large-bandwidth data interaction between FPGAs; the UART module is used for reading, writing and monitoring basic debugging information of the FPGA processing chip; the storage controller is used for controlling an external storage device to finish functions of data storage, initial data loading and the like; the register control module is used for finishing the control and monitoring of the algorithm module.
As shown in fig. 3, the FPGA processing board includes two FPGA processing chips and a RapidIO switch, and mainly completes processing of a core algorithm. The composition of the FPGA processing chip in the FPGA processing board is basically the same as that of the FPGA processing chip in the DSP control board. The FPGA processing chip internally comprises a plurality of functional sub-modules, a soft CPU and a RapidIO bus transceiver module. The functional sub-modules are, for example, Aurora protocol, algorithm processing module, JESD204B protocol, UART module, memory controller, register control module, and the like. The functional sub-module, the soft CPU and the RapidIO bus transceiver module are all mounted on an internal interconnection bus of the FPGA processing chip. And the two FPGA processing chips are bridged by adopting an interconnection bus and are connected with the RapidIO switch inside the FPGA processing board. And the RapidIO switch in each FPGA processing board is connected with the RapidIO switch in the DSP control board through an optical fiber or a back board. The DSP control panel transmits a control command to the FPGA processing panel through the RapidIO switch, the FPGA processing chips are interconnected through an internal bus realized by an Aurora protocol, control information among chips is interacted, and the functions of other components are similar to those of the FPGA processing panel in the DSP control panel.
The DSP control board is used as a main control chip of the electronic countermeasure equipment, controls and processes data of each functional submodule in the FPGA chip in the electronic countermeasure equipment through an interconnection bus, communicates with the display control equipment through a gigabit Ethernet, receives a display control command and outputs a processing result.
The FPGA processing board is internally communicated with each other by adopting a standard interconnection bus, and each functional submodule adopts a uniform bus interface and is mounted on the internal bus to realize the interaction of data and control information. The DSP processing chip is in bridge connection with an FPGA internal bus through a RapidIO bus, so that the DSP processing chip can directly and transparently control each functional submodule in any FPGA processing chip in the electronic countermeasure equipment. Meanwhile, a soft CPU controller is built in each FPGA processing chip and used as a coprocessor of the DSP processing chip to complete initialization and self-checking work of an internal module of the FPGA chip, and a self-checking result is fed back to the DSP processing chip, so that the working pressure of the DSP processing chip is reduced, and the initialization time is shortened.
As shown in fig. 4, after the electronic countermeasure equipment is powered on, the DSP processing chip first completes its own initialization, configures the RapidIO switch in the electronic countermeasure equipment, and determines the node ID of the FPGA processing chip of each network. And after confirming that the configuration state of each node is normal, initializing an internal interconnection bus of the FPGA processing chip and completing address mapping of each functional submodule in the FPGA processing chip. At the moment, the DSP processing core sends an initialization command to the co-processing CPU in each FPGA processing chip in an interruption mode, the co-processing CPU reports the self-checking state of each functional submodule in the FPGA after finishing work, if the self-checking state is normal, the normal working state is entered, otherwise, a module fault code is reported, and the main control judges the next operation or fault removal.
As shown in fig. 5, the internal control flow of the FPGA is initiated by the co-processing CPU, and the co-processing CPU is implemented by using a soft core provided by the FPGA manufacturer. After being powered on, the co-processing CPU receives the initialization interrupt sent by the DSP, firstly releases the reset of each functional sub-module, sequentially controls each functional sub-module to complete self-check, reads the self-check status register of each functional sub-module, and finally summarizes the self-check status and feeds back the status to the DSP. After the self-checking is completed, the initialization parameters required by the FPGA work are loaded from the external storage device, the register required by the algorithm work is configured, and at the moment, the FPGA starts to work normally. And the co-processing CPU enters a monitoring state, monitors the working state of each functional sub-module component and waits for the next working instruction of the DSP processing chip.
In the invention, the number of the universal interconnection boards can be changed, and the number of the boards can be increased or decreased according to the scale of the system. And cooperatively controlling the FPGA array by the RapidIO bus and the EMIF bus. The modules in the FPGA and the FPGA are connected by adopting a high-speed internal interconnection bus, and the interconnection bus protocol may be changed according to requirements, such as an AXI-4 bus or an AVALON bus. And the CPU in the FPGA is adopted to assist the DSP to complete the system work and self-checking flow.
Claims (6)
1. A control framework of a universal electronic countermeasure device comprises a DSP control board and a plurality of FPGA processing boards, and is characterized in that,
the DSP control board comprises a DSP processing chip, an FPGA processing chip and a RapidIO switch; a plurality of functional sub-modules, a co-processing CPU, an EMIF bus transceiver module and a RapidIO bus transceiver module are arranged in the FPGA processing chip; the functional submodule, the coprocessing CPU, the EMIF bus transceiver module and the RapidIO bus transceiver module are all connected with an internal interconnection bus of the FPGA processing chip; the DSP processing chip and the FPGA processing chip adopt a RapidIO bus and an EMIF bus to complete information interaction; the internal interconnection bus of the FPGA processing chip takes three main controls as command initiators, namely a RapidIO bus, an EMIF bus and a co-processing CPU;
the FPGA processing board comprises a plurality of FPGA processing chips and a RapidIO switch; each FPGA processing chip is internally provided with a plurality of functional sub-modules, a co-processing CPU and a RapidIO bus transceiver module; each functional submodule, the coprocessing CPU and the RapidIO bus transceiver module are all connected with an internal interconnection bus of the FPGA processing chip; the FPGA processing chips are bridged by adopting an interconnection bus, and each FPGA processing chip is connected with a RapidIO switch inside the FPGA processing board;
and the RapidIO switch in each FPGA processing board is connected with the RapidIO switch in the DSP control board through an optical fiber or a back board.
2. The universal electronic countermeasure equipment control architecture of claim 1, wherein in the DSP control board a RapidIO bus is used for bandwidth data interaction between the FPGA processing chip and the DSP processing chip; the EMIF bus is used for controlling the receiving and sending of commands; and the co-processing CPU completes the control and initialization of the interior of the FPGA processing chip.
3. The universal electronic countermeasure equipment control architecture of claim 1, wherein in the DSP control board, each of the three masters directly controls each functional sub-module within the FPGA processing chip after being bridged by a RapidIO bus.
4. The universal electronic countermeasure equipment control architecture of claim 1, wherein the functional sub-modules of the FPGA processing chip in the DSP control board and the functional sub-modules of the FPGA processing chip in the FPGA processing board are one or more of Aurora protocol, algorithm processing module, JESD204B protocol, UART module, memory controller, and register control module; the Aurora protocol is used for controlling information interaction between FPGA processing chips; the JESD204B protocol is used for processing bandwidth data interaction between chips by the FPGA; the UART module is used for reading, writing and monitoring debugging information of the FPGA processing chip; the storage controller is used for controlling the external storage device to finish the storage of data and the loading of initialization data; the register control module is used for finishing the control and monitoring of the algorithm processing module.
5. The universal electronic countermeasure equipment control architecture of claim 1, wherein after the electronic countermeasure equipment is powered on, the DSP processing chip first completes its own initialization, configures each RapidIO switch in the electronic countermeasure equipment and determines the node ID of each networked FPGA processing chip; after confirming that the configuration state of each node is normal, initializing an internal interconnection bus of each FPGA processing chip, and completing address mapping of each functional sub-module in each FPGA processing chip; the DSP processing chip sends an initialization command to the co-processing CPU in each FPGA processing chip in an interrupt mode, the co-processing CPU reports the self-checking state of each functional submodule in the FPGA processing chip after finishing work, if the self-checking state is normal, the DSP processing chip enters a normal working state, and otherwise, a fault code is reported.
6. The control architecture of the universal electronic countermeasure equipment as claimed in claim 1, wherein the internal control flow of the FPGA is initiated by the co-processing CPU, and after the co-processing CPU receives an initialization command sent by the DSP processing chip, the co-processing CPU first releases the reset of each functional sub-module, sequentially controls each functional sub-module to complete self-checking, reads the self-checking status register of each functional sub-module, and finally summarizes the self-checking status and feeds back to the DSP processing chip; after self-checking is completed, loading initialization parameters required by FPGA work from an external storage device, and configuring a register required by algorithm work; after the FPGA processing chip starts to work normally, the co-processing CPU enters a monitoring state, monitors the working state of each functional sub-module component and waits for the next working instruction of the DSP processing chip.
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| CN112148651B (en) * | 2020-10-10 | 2022-05-03 | 中国人民解放军国防科技大学 | Enhanced rapidio interconnection device and equipment |
| CN112613264A (en) * | 2020-12-25 | 2021-04-06 | 南京蓝洋智能科技有限公司 | Distributed extensible small chip design framework |
| CN112788445A (en) * | 2020-12-30 | 2021-05-11 | 华清瑞达（天津）科技有限公司 | High-speed low-delay optical fiber switching system and method |
| CN114116547B (en) * | 2021-11-12 | 2024-03-26 | 成都立思方信息技术有限公司 | Reconfigurable electronic countermeasure equipment simulator architecture |
| CN115766269A (en) * | 2022-11-25 | 2023-03-07 | 郑州大学 | Multi-network isolation gatekeeper exchange unit based on RapidIO |
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