CN109510601B - Switched capacitor subtracting circuit and sensor device - Google Patents
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- CN109510601B CN109510601B CN201710828525.8A CN201710828525A CN109510601B CN 109510601 B CN109510601 B CN 109510601B CN 201710828525 A CN201710828525 A CN 201710828525A CN 109510601 B CN109510601 B CN 109510601B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 156
- 238000005070 sampling Methods 0.000 claims description 46
- 238000007599 discharging Methods 0.000 claims description 4
- 230000010354 integration Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 1
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- 230000000750 progressive effect Effects 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
- H03F3/45968—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction
- H03F3/45973—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction by using a feedback circuit
- H03F3/45977—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction by using a feedback circuit using switching means, e.g. sample and hold
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45012—Indexing scheme relating to differential amplifiers the addition of two signals being made in a switched capacitor circuit for producing the common mode signal
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Abstract
A switched capacitor subtraction circuit and a sensor apparatus, the circuit comprising: an operational amplifier having a non-inverting input terminal connected to a reference voltage; the first capacitor circuit is connected with a first input signal and the reference voltage, and the output end of the first capacitor circuit has a first polarity; the second capacitor circuit is connected with a second input signal and the reference voltage, and the output end of the second capacitor circuit is provided with a second polarity opposite to the first polarity; an integrating capacitor; wherein there is a difference between the first input signal and the second input signal, the first capacitance circuit and the second capacitance circuit are simultaneously discharged to each transfer the stored charge to the integrating capacitance. The common mode subtraction is achieved by separately collecting two input signals having differences and simultaneously transferring the stored charges to the integrating capacitors in opposite polarities.
Description
Technical Field
The invention belongs to the technical field of switch capacitors, and particularly relates to a switch capacitor subtracting circuit and sensor equipment.
Background
Some electronic systems may include signal paths for processing signals. For example, the biometric system may include an Integrated Circuit (IC) having a signal path for processing signals received from the biometric sensor. The signal path may have common mode errors that may be generated by various sources, such as common mode noise and/or systematic deviations associated with the signal path. Common mode errors can reduce the integrity of data processed using the signal path.
For example, in a biometric system implementation, common mode errors of the signal channels may produce progressive mode errors that cause visual artifacts in the biometric image produced using the biometric system. In certain applications, common mode errors are reduced by using differential signals, by increasing circuit area or power consumption, etc., but none are a reasonable solution.
Disclosure of Invention
The invention aims to provide a switched capacitor subtracting circuit and sensor equipment, and aims to solve the problem that a scheme for reducing common mode errors is unreasonable in the traditional technical scheme.
A switched capacitor subtraction circuit, the circuit comprising:
An operational amplifier having a non-inverting input terminal connected to a reference voltage;
The output end of the first capacitor circuit is connected with the inverting input end of the operational amplifier and has a first polarity;
The second capacitor circuit is connected with a second input signal and the reference voltage, and the output end of the second capacitor circuit is connected with the output end of the first capacitor circuit and has a second polarity opposite to the first polarity; and
The integrating capacitor is connected between the inverting input end and the output end of the operational amplifier;
Wherein there is a difference between a first input signal and the second input signal, the first capacitive circuit and the second capacitive circuit being configured to: and simultaneously discharging to transfer the stored electric quantity to the integrating capacitor.
Preferably, the first capacitor circuit includes a first capacitor, and when the first capacitor is charged, a first end of the first capacitor loads the first input signal, and a second end loads the reference voltage; when the first capacitor discharges, the second end of the first capacitor loads the reference voltage, and the first end of the first capacitor discharges as the output end of the first capacitor circuit.
Preferably, the second capacitor circuit includes a second capacitor, and when the second capacitor is charged, a first end of the second capacitor loads the second input signal, and a second end loads the reference voltage; when the second capacitor discharges, the first end loads the reference voltage, and the second end discharges as the output end of the second capacitor circuit.
Preferably, the first capacitor circuit further comprises a first sampling capacitor, a first switch, a second switch, a third switch and a fourth switch, wherein:
The first end of the first sampling capacitor is connected with the first input signal through the first switch, the first end of the first sampling capacitor is connected with one end of the second switch, the second end of the first sampling capacitor is connected with the reference voltage through the third switch and the fourth switch respectively, and the other end of the second switch is used as the output end of the first capacitor circuit;
The first switch and the fourth switch are controlled by a first switch signal, and the second switch and the fourth switch are controlled by a second switch signal interleaved with the first switch signal.
Preferably, the second capacitance circuit further includes a second sampling capacitor, a fifth switch, a sixth switch, a seventh switch, and an eighth switch, wherein:
the first end of the second sampling capacitor is connected with the second input signal through the fifth switch, the first end of the second sampling capacitor is also connected with the reference voltage through the sixth switch, the second end of the second sampling capacitor is connected with the reference voltage through the eighth switch, the second end of the second sampling capacitor is connected with one end of the seventh switch, and the second end of the seventh switch is used as the output end of the second capacitance circuit;
the fifth and eighth switches are controlled by the first switch signal, and the sixth and seventh switches are controlled by the second switch signal.
Preferably, the circuit further comprises a ninth switch controlled by the first switch signal, and the ninth switch is connected in parallel with the integrating capacitor.
Preferably, the first sampling capacitor and the second sampling capacitor have the same capacity.
In addition, a sensor device is provided, comprising the switched capacitor subtracting circuit.
The switched capacitor subtraction circuit realizes common mode subtraction by respectively acquiring two input signals with difference values and simultaneously transferring stored charges to an integrating capacitor in a mode of opposite polarities. And gain adjustment of the signal difference is realized by setting different ratio relations of integrating capacitance and capacitance of the capacitance circuit.
Drawings
FIG. 1 is a schematic diagram of a switched capacitor subtracting block diagram according to a preferred embodiment of the present invention;
Fig. 2 is a diagram of input signals, switching signal timings, and output signals of the switched capacitor subtracting circuit shown in fig. 1.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Fig. 1 shows a switched capacitor subtracting circuit applicable to a sensor device such as a fingerprint sensor according to a preferred embodiment of the present invention, wherein the circuit includes an operational amplifier OP1, a first capacitor circuit 10, a second capacitor circuit 20 and an integrating capacitor Cint.
The non-inverting input end +ip of the operational amplifier OP1 is connected with the reference voltage VRF; the first capacitor circuit 10 is connected to the first input signal IN0 and the reference voltage VRF, and the output terminal 101 of the first capacitor circuit 10 is connected to the inverting input terminal-IN of the operational amplifier OP1 and has a first polarity. The second capacitor circuit 20 is connected to the second input signal IN1 and the reference voltage VRF, and the output terminal 201 of the second capacitor circuit 20 is connected to the inverting input terminal-IN of the operational amplifier OP1 (the output terminal 101 of the first capacitor circuit 10) and has a second polarity opposite to the first polarity; the integrating capacitor Cint is connected between the inverting input terminal-In and the output terminal OUT of the operational amplifier OP 1; wherein there is a difference between the first input signal IN0 and the second input signal IN1, the first capacitance circuit 10 and the second capacitance circuit 20 are configured to: simultaneously discharging to transfer the stored charge to the integrating capacitor Cint such that the charge of the integrating capacitor Cint is the difference between the absolute values of the discharge of the first and second capacitor circuits 10, 20, such that the two opposite-polarity capacitor circuits 10, 20 charge the integrating capacitor Cint simultaneously through a common junction (-In terminal) at which the common mode signal between the first and second input signals In0, in1 is cancelled.
It will be appreciated that the integration capacitor Cint needs to be short-circuited during the charging phase of the first and second capacitor circuits 10, 20, and the integration capacitor Cint is turned on during the discharging phase of the first and second capacitor circuits 10, 20.
IN this embodiment, the first capacitor circuit 10 includes a first capacitor Ci0, and when the first capacitor Ci0 is charged, a first end thereof loads a first input signal IN0, and a second end thereof loads a reference voltage VRF; when the first capacitor Ci0 is discharged, the second terminal is applied with the reference voltage VRF, and the first terminal is discharged as the output terminal 101 of the first capacitor circuit 10. The second capacitor circuit 20 includes a second capacitor Ci1, and when the second capacitor Ci1 is charged, a first end thereof loads a second input signal IN1 and a second end thereof loads a reference voltage VRF; when the second capacitor Ci1 is discharged, the first terminal is supplied with the reference voltage VRF, and the second terminal is discharged as the output terminal 201 of the circuit 20 of the second capacitor Ci 1. It is understood that the capacity of the first capacitor Ci0 and the capacity of the second capacitor Ci1 are equal, and C is set. In addition, the capacity cint=n×c of the integration capacitance Cint, n being a coefficient. The signal difference between the first input signal IN0 and the second input signal IN1 is amplified when n is less than 1, and compressed when n is greater than 1. I.e. the signal difference may be scaled up, down and of the original size depending on the value of n.
Referring to fig. 1 and 2, in a more specific embodiment, the first capacitor circuit 10 includes a first sampling capacitor Ci0, a first switch s1, a second switch s2, a third switch s3, and a fourth switch s4.
A first end of the first sampling capacitor Ci0 is connected with a first input signal IN0 through a first switch s1, the first end of the first sampling capacitor Ci0 is connected with one end of a second switch s2, a second end of the first sampling capacitor Ci0 is connected with a reference voltage VRF through a third switch s3 and a fourth switch s4 respectively, and the other end of the second switch s2 is used as an output end 101 of the first capacitor circuit 10; the first switch s1 and the fourth switch s4 are controlled by the first switch s1 signal, and the second switch s2 and the fourth switch s4 are controlled by the second switch signal P1n interleaved with the first switch signal P1.
The second capacitance circuit 20 further includes a second sampling capacitance Ci1, a fifth switch s5, a sixth switch s6, a seventh switch s7, and an eighth switch s8.
The first end of the second sampling capacitor Ci1 is connected to the second input signal IN1 through a fifth switch s5, the first end of the second sampling capacitor Ci1 is also connected to the reference voltage VRF through a sixth switch s6, the second end of the second sampling capacitor Ci1 is connected to the reference voltage VRF through an eighth switch s8, the second end of the second sampling capacitor Ci1 is connected to one end of a seventh switch s7, and the second end of the seventh switch s7 is used as the output end 201 of the second capacitor circuit 20; the fifth switch s5 and the eighth switch s8 are controlled by the first switching signal P1, and the sixth switch s6 and the seventh switch s7 are controlled by the second switching signal P1 n. Preferably, the circuit further comprises a ninth switch controlled by the first switch signal P1, and the ninth switch is connected in parallel with the integrating capacitor Cint.
It can be understood that the first sampling capacitor Ci0 is the first capacitor Ci0, and the second sampling capacitor Ci1 is the second capacitor Ci1; the switch can be realized by a MOS tube or a triode.
Referring to fig. 1 and 2, IN a more detailed embodiment, the output signal range is related to the difference between the first input signal IN0 and the second input signal IN1, independent of their common mode signals.
The difference signal of the first input signal IN0 and the second input signal IN1 may set the difference gain by adjusting the integrating capacitance Cint.
First, during the signal sampling and difference integration phase, we draw the following conclusions through charge conservation:
OUT＝VRF+(IN0-IN1)×C/Cint＝VRF+(IN0-IN1)×C/(n×C)
＝VRF+(IN0-IN1)/n.
It can be seen that the signal difference is amplified when n is less than 1 and compressed when n is greater than 1. I.e. the signal difference may be scaled up, down and of the original size depending on the value of n.
Let ci0=ci1=cint=c.
1. First duty cycle:
In the high level period of the first switching signal P1, the charges on the sampling capacitances Ci0 and Ci1 and the integration capacitance Cint are respectively:
Qi0＝[(VCM-3)-VRF]×Ci0＝[(VCM-3)-VRF]×C；
Qi1＝[(VCM+2)-VRF]×Ci1＝[(VCM+2)-VRF]×C；
in the high level period of the first switching signal P1, the integrating capacitor Cint is shorted at both ends, qint=0;
Wherein VCM is a common mode signal, and the numerical parameters (e.g. 2, 3) are voltage values.
In the high level period of the second switching signal P1n, due to the operational amplifier characteristic, the voltages in≡ip across the operational amplifier OP1 are caused to transfer the stored charges on the sampling capacitors Ci0 and Ci1 to the integrating capacitor Cint, and since two of the storage capacitors are interposed In opposite polarities at the inverting input terminal-In of the operational amplifier OP1, the equivalent charge Qtotal at the-In terminal before the charges are transferred to the integrating capacitor Cint is:
qtotal=qi0' +qi1″= -5×c; (it can be seen that the common mode signal VCM is removed)
Wherein Qi0 "= [ (VCM-3) -VRF ] ×c0= [ (VCM-3) -VRF ] ×c;
Wherein Qi1 "= - [ (vcm+2) -VRF ] ×c0= - [ (vcm+2) -VRF ] ×c;
Equivalent charge at-In terminal after charge transfer to integrating capacitor Cint:
Qint`＝(VRF-OUT)×C；
The charge amount before and after transfer is the same:
qtotal = Qint', i.e.: -5 xc= (VRF-OUT) xc;
the following steps are obtained: out=vrf+5.
2. Duty cycle 2
In the high level period of the first switching signal P1, the charges on the sampling capacitances Ci0 and Ci1 and the integration capacitance Cint are respectively:
Qi0＝[(VCM+2)-VRF]×Ci0＝[(VCM+2)-VRF]×C；
Qi1＝[(VCM-2)-VRF]×Ci1＝[(VCM-2)-VRF]×C；
in the high level period of the first switching signal P1, the integrating capacitor Cint is shorted at both ends, qint=0;
In the high level period of the second switching signal P1n, in≡ip will be caused due to the operational amplifier characteristic, so that the charges stored In the sampling capacitors Ci0 and Ci1 are transferred to the integrating capacitor Cint, and since two of the storage capacitors are interposed at the-In terminal with opposite polarities, the equivalent charges at the-In terminal before the charges are transferred to the integrating capacitor Cint:
qtotal=qi0' +qi1j=4×c; (it can be seen that the common mode signal VCM is removed)
Qi0`＝[(VCM+2)-VRF]×Ci0＝[(VCM+2)-VRF]×C；
Qi1`＝-[(VCM-2)-VRF]×Ci0＝-[(VCM-2)-VRF]×C；
Equivalent charge at-In terminal after charge transfer to integrating capacitor Cint:
Qint`＝(VRF-OUT)×C；
The charge amount before and after transfer is the same:
qtotal = Qint', i.e.: 4 xc= (VRF-OUT) ×c;
The following steps are obtained: out=vrf-4.
3. Third working period
In the high level period of the first switching signal P1, the charges on the sampling capacitances Ci0 and Ci1 and the integration capacitance Cint are respectively:
Qi0＝[(VCM-2)-VRF]×Ci0＝[(VCM-2)-VRF]×C；
Qi1＝[(VCM+2)-VRF]×Ci1＝[(VCM+2)-VRF]×C；
in the high level period of the first switching signal P1, the integrating capacitor Cint is shorted at both ends, qint=0;
In the high level period of the second switching signal P1n, in≡ip will be caused due to the operational amplifier characteristic, so that the charges stored In the sampling capacitors Ci0 and Ci1 are transferred to the integrating capacitor Cint, and since two of the storage capacitors are interposed at the-In terminal with opposite polarities, the equivalent charges at the-In terminal before the charges are transferred to the integrating capacitor Cint:
qtotal=qi0' +qi1″= -4×c; (common mode Signal VCM is removed)
Qi0`＝[(VCM-2)-VRF]×Ci0＝[(VCM-2)-VRF]×C；
Qi1`＝-[(VCM+2)-VRF]×Ci0＝-[(VCM+2)-VRF]×C；
Equivalent charge at-In terminal after charge transfer to integrating capacitor Cint:
Qint`＝(VRF-OUT)×C；
The charge amount before and after transfer is the same:
qtotal = Qint', i.e.: -4 xc= (VRF-OUT) xc;
The following steps are obtained: out=vrf+4.
From the above calculation, we can clearly see that the processing by this circuit can realize the going-out of the common mode signal of the input signal and the difference processing of the input signal. In this way, the common-mode subtraction is achieved by separately collecting two input signals having differences, and simultaneously transferring the stored charges to the integrating capacitor Cint in opposite polarities. And gain adjustment of the signal difference is realized by setting different ratio relations of the integrating capacitor Cint and the capacity of the capacitor circuit.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (6)
1. A switched capacitor subtraction circuit, the circuit comprising:
An operational amplifier having a non-inverting input terminal connected to a reference voltage;
The output end of the first capacitor circuit is connected with the inverting input end of the operational amplifier and has a first polarity;
The second capacitor circuit is connected with a second input signal and the reference voltage, and the output end of the second capacitor circuit is connected with the output end of the first capacitor circuit and has a second polarity opposite to the first polarity; and
The integrating capacitor is connected between the inverting input end and the output end of the operational amplifier;
Wherein there is a difference between a first input signal and the second input signal, the first capacitive circuit and the second capacitive circuit being configured to: simultaneously discharging to transfer the stored electrical quantity to the integrating capacitor;
the first capacitor circuit comprises a first sampling capacitor, a first switch, a second switch, a third switch and a fourth switch, wherein:
The first end of the first sampling capacitor is connected with the first input signal through the first switch, the first end of the first sampling capacitor is connected with one end of the second switch, the second end of the first sampling capacitor is connected with the reference voltage through the third switch and the fourth switch respectively, and the other end of the second switch is used as the output end of the first capacitor circuit;
The first switch and the fourth switch are controlled by a first switch signal, and the second switch and the fourth switch are controlled by a second switch signal which is staggered with the first switch signal;
The second capacitor circuit comprises a second sampling capacitor, a fifth switch, a sixth switch, a seventh switch and an eighth switch, wherein:
the first end of the second sampling capacitor is connected with the second input signal through the fifth switch, the first end of the second sampling capacitor is also connected with the reference voltage through the sixth switch, the second end of the second sampling capacitor is connected with the reference voltage through the eighth switch, the second end of the second sampling capacitor is connected with one end of the seventh switch, and the second end of the seventh switch is used as the output end of the first capacitor circuit;
the fifth and eighth switches are controlled by the first switch signal, and the sixth and seventh switches are controlled by the second switch signal.
2. The switched capacitor subtraction circuit as claimed in claim 1, wherein when said first sampling capacitor is charged, a first terminal thereof is loaded with said first input signal, and a second terminal thereof is loaded with said reference voltage; when the first sampling capacitor discharges, the second end of the first sampling capacitor loads the reference voltage, and the first end of the first sampling capacitor discharges as the output end of the first capacitor circuit.
3. The switched capacitor subtracting circuit as claimed in claim 1 or 2, wherein said second sampling capacitor is charged with said second input signal at a first terminal and said reference voltage at a second terminal; when the second sampling capacitor discharges, the first end loads the reference voltage, and the second end discharges as the output end of the second capacitor circuit.
4. The switched-capacitor subtracting circuit of claim 1 further comprising a ninth switch controlled by said first switch signal, said ninth switch being in parallel with said integrating capacitor.
5. The switched-capacitor subtracting circuit of claim 1 wherein the first sampling capacitor and the second sampling capacitor have the same capacitance.
6. A sensor device comprising the switched capacitor subtraction circuit of any one of claims 1 to 5.
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Country or region after: China Address after: 336000 No.133, Yishang Avenue, Yichun economic and Technological Development Zone, Jiangxi Province Applicant after: Jiangxi Zhixin Intelligent Technology Co.,Ltd. Address before: 518000 room 1007, scientific research building, Tsinghua information port, North District, high tech Industrial Park, Nanshan District, Shenzhen, Guangdong Applicant before: SHENZHEN FINGERCHIP INTELLIGENT TECHNOLOGY Co.,Ltd. Country or region before: China |
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| GR01 | Patent grant |