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CN108964876B - Ordinary round conversion arithmetic unit, ordinary round conversion circuit and AES encryption circuit - Google Patents

Ordinary round conversion arithmetic unit, ordinary round conversion circuit and AES encryption circuit Download PDF

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CN108964876B
CN108964876B CN201810597109.6A CN201810597109A CN108964876B CN 108964876 B CN108964876 B CN 108964876B CN 201810597109 A CN201810597109 A CN 201810597109A CN 108964876 B CN108964876 B CN 108964876B
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张肖强
王维
郑辛星
郑群现
王宸宇
王广亮
刘宇畅
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Anhui Polytechnic University
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Abstract

The invention is suitable for the technical field of encryption, and provides a common round transformation operation unit, a common round transformation circuit and an AES encryption circuit.

Description

Ordinary round conversion arithmetic unit, ordinary round conversion circuit and AES encryption circuit
Technical Field
The invention belongs to the technical field of encryption, and provides a common round conversion operation unit, a common round conversion circuit and an AES encryption circuit.
Background
AES (Advanced Encryption Standard) is a new generation of block symmetric cipher algorithm established by the national institute of standards and technology 2001, and is used to replace the original DES (Data Encryption Standard).
At present, the AES cipher algorithm is adopted by a plurality of international standards organizations, and is the most widely used block cipher algorithm at present, the data block length of the AES cipher algorithm is 128 bits, the key length is 128 bits, 192 bits and 256 bits, which are respectively called AES-128, AES-192 and AES-256, the AES algorithm is an iterative algorithm, each iteration can be called round conversion, the key length is different, the number of round conversion is also different, and the number of round conversion Nr of the AES-128, AES-192 and AES-256 is respectively 10, 12 and 14.
The AES encryption process is as shown in fig. 1, the input plaintext data sequentially performs a first round of transformation, Nr-1 round of normal round of transformation, and last round of transformation, the normal round of transformation operation is a main operation in the AES encryption process, each time the normal round of transformation needs to sequentially perform four operations of byte replacement, row shift, column mixing, and key addition, four operation units corresponding to the four operations sequentially and individually operate, the normal round of transformation circuit based on the four operation units individually operates not only wastes circuit resources, but also has a long key path, and therefore, several adjacent operation units are combined into one operation unit through a synthesis matrix to be implemented.
The T box realizes that the operation results of operations such as S box, row shift, column mixing and the like are prestored in a storage operation unit in a precalculation mode, and the functions of S box, row shift, column mixing and merging operations are realized in a look-up table mode. The T box implementation reduces the critical path of the whole round conversion circuit, so the T box implementation mode is mainly applied to the high-speed AES circuit design, although the T box implementation mode can accelerate the data processing speed, the circuit area is greatly increased, for example, Rach et al will be based on the last GF (2) in the composite domain S box/inverse S box4) The method comprises the steps that five operations such as a multiplier, a mapping matrix/inverse mapping operation, an affine/inverse affine operation, a column mixing/inverse column mixing operation and a key addition operation are combined into an operation unit, the combined operation unit shortens a circuit critical path, but greatly increases the circuit area, and in the existing published documents, the proposed operation unit combination optimizes the length of the critical path at the cost of increasing the circuit area.
Disclosure of Invention
The embodiment of the invention provides an AES encrypted common round conversion circuit, aiming at solving the problem that the lengths of key paths are optimized at the cost of increasing the circuit area in the combination of operation units of the existing common round conversion circuit.
The present invention is achieved as described above, in a general round conversion operation unit for AES encryption, the general round conversion operation unit including:
a synthetic matrix multiplication unit 1 having an input terminal connected to the data input port; the input end of the composite domain multiplication inverse operation unit is connected with the output end of the synthetic matrix multiplication operation unit 1; a synthetic matrix multiplication unit 2 with an input end connected with the output end of the composite domain multiplication inverse operation unit and the key input port; a constant addition operation unit with an input end connected with the output end of the synthetic matrix multiplication operation unit 2, and an output end connected with the data output port, wherein,
the composite matrix multiplication unit 1 inputs a four-byte column vector D from a data input portv＝[d0,d1,d2,d3]TCombining the matrix delta with the column vector DvPerforming multiplication to obtain a matrix Lv＝[l0,l1,l2,l3]TAnd outputting the data to a composite domain multiplication inverse operation unit, wherein the expression of the synthesis matrix delta is as follows:
Figure BDA0001692055860000021
a complex domain inverse multiplication unit for multiplying Lv＝[l0,l1,l2,l3]TEach byte in the array is subjected to complex domain multiplication inverse operation, and a matrix I after the complex domain multiplication inverse operation is performedv＝[i0,i1,i2,i3]TOutput to the synthesis matrix multiplication unit 2;
a composite matrix multiplication unit 2 for combining the matrix Iv＝[i0,i1,i2,i3]TAnd a key vector K input from the key input portv＝[k0,k1,k2,k3]TAre combined into a column vector pv＝[i0,i1,i3,k0,k1,k2,k3]TSynthesizing the matrix Lambda with the column vector pvPerforming multiplication to obtain a matrix Qv＝[q0,q1,q2,q3]TAnd outputting to a constant addition operation unit, wherein the synthetic matrix lambda is expressed as follows:
Figure BDA0001692055860000031
a constant addition unit for adding the matrix Qv＝[q0,q1,q2,q3]TAnd constant vector omegav＝[ω,ω,ω,ω]TAddition operation, matrix R after addition operationv＝[r0,r1,r2,r3]TOutputting from a data output port, wherein the constant ω is a byte constant specified by an affine operation in the AES S box;
the data bit widths of the data input end and the data output end of the synthesis matrix multiplication arithmetic unit 1, the composite domain multiplication inverse arithmetic unit, the synthesis matrix multiplication arithmetic unit 2 and the constant addition arithmetic unit are all 4 bytes, and the data bit width of the key input port is all 4 bytes.
The invention also provides a common wheel conversion circuit which consists of 4 x (N)r-1) a common round transform arithmetic unit,
wherein, every 4 ordinary round conversion arithmetic units are connected in parallel to form an ordinary round conversion module for finishing an ordinary round conversion operation, (N)r-1) a common wheel conversion module is connected in series to form a common wheel conversion circuit.
The present invention also provides a common wheel converting circuit, including: an ordinary round conversion operation unit, and a method for circulating 4 × (N)r-1) a loop feedback circuit of said ordinary round transform arithmetic unit;
the circular feedback circuit consists of a selector, a register 1 and a register 2, wherein the input end of the register 1 is connected with the output end of the selector, the output end of the register 1 is connected with the input end of the register 2, the output end of the register 2 is connected with the input end of the ordinary round transformation operation unit, the output end of the ordinary round transformation operation unit is connected with one input end of the selector, the other input end of the selector is connected with the output end of the first round transformation circuit, and the output end of the ordinary round transformation operation unit is also connected with the input end of the last round transformation circuit;
the data bit width of the register 1 and the register 2 is 16 bytes.
The present invention also provides a common wheel conversion circuit, including: a common wheel transformation module formed by connecting two common wheel transformation operation units in parallel, and a circular feedback circuit for carrying out 2 (N) on the common wheel transformation moduler-1) a cycle;
the circular feedback circuit consists of a selector, a register 1 and a register 2, wherein the input end of the register 1 is connected with the output end of the selector, the output end of the register 1 is connected with the input end of the register 2, the output end of the register 2 is connected with the input end of the common wheel conversion module, the output end of the first wheel conversion circuit is connected with one input end of the selector, the other input end of the selector is connected with the output end of the common wheel conversion module, and the output end of the common wheel conversion module is also connected with the input end of the last wheel conversion circuit;
the data bit width of the register 1 and the register 2 is 16 bytes.
The present invention also provides a common wheel conversion circuit, including: a common wheel transformation module formed by four common wheel transformation operation units connected in parallel, and a circular feedback circuit for carrying out (N) on the common wheel transformation moduler-1) a cycle;
the circular feedback circuit consists of a selector and a register, the output end of the register is connected with the input end of the common wheel conversion module, the input end of the register is connected with the output end of the selector, one input end of the selector is connected with the output end of the first wheel conversion circuit, the other input end of the selector is connected with the output end of the corresponding common wheel conversion module, and the output end of the common wheel conversion operation module is also connected with the input end of the last wheel conversion circuit;
the data bit width of the register is 16 bytes.
The present invention also provides an AES encryption circuit, including:
a first-wheel conversion circuit, a common-wheel encryption circuit and a last-wheel conversion circuit which are connected in series in sequence.
The common round transformation operation unit for AES encryption combines all linear transformation operations of the common round transformation operation into two synthetic matrixes through the combination and synthesis operation of constant matrixes, and synthesizes the matrix delta and the synthetic matrix lambda, so that the key path of a common round transformation circuit is shortened, and the realization area of the common round transformation circuit is reduced.
Drawings
Fig. 1 is a flowchart of a standard AES encryption provided by an embodiment of the present invention;
FIG. 2 is a schematic diagram of a conventional round conversion unit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a general wheel conversion circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a general wheel conversion circuit according to a second embodiment of the present invention;
fig. 5 is a schematic structural diagram of a general wheel conversion circuit according to a third embodiment of the present invention;
fig. 6 is a schematic structural diagram of a general wheel conversion circuit according to a fourth embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The conventional arithmetic unit includes: a byte replacement operation unit, a row shift operation unit, a column mixing operation unit and a key addition operation unit, wherein the operation formula of the operation unit is as follows
1. Byte replacement arithmetic unit
The byte replacement operation unit performs byte replacement operation, generally called S-box operation, where each byte in the state matrix is replaced according to a byte replacement table, and it is assumed that the input state matrix of the ordinary round transform operation is:
Figure BDA0001692055860000051
the state matrix after the S-box operation is:
Figure BDA0001692055860000061
the S-box operation can be expressed as:
Figure BDA0001692055860000062
where S () is an S-box arithmetic function. The S-box operation is the only nonlinear operation in the four round conversion operations and is also the operation with the highest operation complexity, so that the S-box circuit occupies most of the area and power consumption of the whole AES circuit.
In AES S-Box operation, the input byte is first subjected to a finite field GF (2)8) The inverse operation of multiplication on the domain is carried out, and then an affine operation is carried out, wherein the expression is as follows:
Figure BDA0001692055860000063
where x is the input byte, ()A -1Is GF (2)8) The multiplication inverse operation on the domain, τ is an 8 × 8bit constant matrix, ω is a byte constant, and τ and ω are used to complete affine operations in the S-box.
GF (2) according to the present invention8) The field is GF (2) specified in AES cipher algorithm8) Field, irreducible polynomial of
f(x)＝x8+x4+x3+x+1
The constant matrix τ and the byte constant ω are:
Figure BDA0001692055860000064
among many S-box implementations, the composite domain based S-box implementation has the smallest circuit area. Composite domain S-box transforms the principal arithmetic unit-GF (2) in the S-box by mathematical transformation8) The inverse domain multiplication unit maps to the complex domain implementation. The computational complexity of the complex domain multiplicative inverse is much less than GF (2)8) The computational complexity of the inverse of the domain multiplication can be reduced significantly, thus the hardware complexity of the S-box circuit implementation can be reduced significantly.
The AES S box operation expression based on the composite domain is as follows:
Figure BDA0001692055860000071
wherein ()C -1For multiplicative inverse operations on complex fields, the complex field being an arbitrary and GF (2)8) Composite domain of domain isomorphism, delta is 8 x 8bit mapping matrix, whose function is to convert input byte x from GF (2)8) The field is mapped to the complex field, δ' is the δ inverse matrix, which acts to map the complex field multiplicative inverse result from the complex field back to GF (2)8) A domain.
In the finite field, the addition operation is a bit exclusive or logic operation. According to
Figure BDA0001692055860000074
Therefore, when the constant addition operation + ω is implemented in hardware, the addition 0 operation can be directly omitted, and the addition 1 operation can replace the exclusive or logic operation by two methods: 1. the exclusive or logic of any two variables is replaced by the exclusive or logic; 2. the two variables are realized by using exclusive-OR logic and inverting logic. Because the circuit area and the time delay of the exclusive-OR gate and the exclusive-OR gate are almost the same, and compared with the exclusive-OR gate, the circuit area and the time delay of the reverse logic gate can be ignored, therefore, when the S box is realized by hardwareThe area and the time delay of the constant plus operation + omega circuit can be ignored.
2. Line shift arithmetic unit
The line shift operation unit performs a line shift operation, which is a simple operation in which the first line of the state matrix is not transformed, and the second, third, and fourth lines are shifted to the left by one byte, two bytes, and three bytes, respectively. Assume that the state matrix after the row shift operation is:
Figure BDA0001692055860000073
the state matrix after row shifting can be expressed as:
Figure BDA0001692055860000081
in the hardware implementation, the line shift operation does not need to consume any logic circuit resource, and the line shift operation can be realized only by adjusting the bus position.
3. Column mix arithmetic unit
The column mix operation unit performs a mixed column operation in which each column of the state matrix can be regarded as a cubic polynomial on the ring R, and the column mix operation is defined as a product of each column polynomial of the state matrix and a constant polynomial on the ring R. Assume that the state matrix after column mixing operation is:
Figure BDA0001692055860000082
the expression for the column mix operation is:
Figure BDA0001692055860000083
wherein the matrix phi is a column mixing constant matrix of
Figure BDA0001692055860000084
Are each GF (2)8) Domain multiplication by the constant x {03}16、×{02}16、×{01}16In matrix form, in the present invention { }16Representing a hexadecimal form of the constant.
4. Key addition unit
The key addition unit performs a key addition operation, which is also a very simple operation, and is defined as a state matrix plus a sub-key matrix, where the addition operation is GF (2) -field addition, i.e., a bit exclusive or operation. Assume that the state matrix after the key addition operation is:
Figure BDA0001692055860000091
the key addition operation expression is:
Figure BDA0001692055860000092
the matrix K is a sub-key matrix, the sub-key matrix is generated by an input original key through a key expansion algorithm, and the sub-key matrix is also a 4 x 4 byte matrix.
The four arithmetic units in the round conversion can be realized independently, or several adjacent arithmetic units can be combined into one arithmetic unit for realization. The round conversion circuit realized by the arithmetic unit independently wastes circuit resources and has a long critical path. The invention combines linear operations in wheel transformation through combination and synthesis operation of constant matrixes according to a wheel transformation formula. According to the sub-operation formulas in the middle-wheel transformation, the common wheel transformation formula in the wheel transformation can be obtained as follows:
Figure BDA0001692055860000093
output variable r having the same input in the above formulax,yDividing into one group, each column of output variables can form one group, and the above formula can be divided into four groups. These four groups have the same arithmetic operation and have the same circuit arithmetic unit when implemented in hardware. Each packet output variable can be expressed in the form of a linear equation:
Figure BDA0001692055860000094
the corresponding variables in each group of input variables and output variables in the above equation are:
Figure BDA0001692055860000101
Figure BDA0001692055860000102
in order to reduce the circuit implementation area, the invention further uses GF (2) in the S box8) The multiplication is inversely mapped to a composite domain, and the general round transformation grouping formula after mapping is as follows:
Figure BDA0001692055860000103
the common round transformation operation unit for AES encryption combines all linear transformation operations of the common round transformation operation into two synthetic matrixes through the combination and synthesis operation of constant matrixes, and synthesizes the matrix delta and the synthetic matrix lambda, so that the key path of a common round transformation circuit is shortened, and the realization area of the common round transformation circuit is reduced.
Fig. 2 is a schematic structural diagram of a general round conversion operation unit according to an embodiment of the present invention, and for convenience of description, only the parts related to the embodiment of the present invention are shown.
The ordinary round conversion arithmetic unit is a minimum unit for forming an ordinary round conversion circuit, and comprises:
a synthetic matrix multiplication unit 1 having an input terminal connected to the data input port; the input end of the composite domain multiplication inverse operation unit is connected with the output end of the synthetic matrix multiplication operation unit 1; a synthetic matrix multiplication unit 2 with an input end connected with the output end of the composite domain multiplication inverse operation unit and the key input port; a constant addition operation unit with input end connected with output end of the synthetic matrix multiplication operation unit 2 and output end connected with data output port, wherein
The synthetic matrix multiplication unit 1 has 4-byte data bit widths at the input and output ends, and inputs four-byte column vector D from the data input portv＝[d0,d1,d2,d3]TCombining the matrix delta with the column vector DvMultiplication is carried out, the composite matrix delta is formed by combining four constant matrixes delta, the constant matrixes delta are mapping matrixes, and GF (2) is used8) Elements on the field map to the composite field, GF (2) in embodiments of the present invention8) The field is GF (2) specified in AES cipher algorithm8) The expression of the domain, composition matrix Δ is as follows:
Figure BDA0001692055860000111
the multiplication expression by the synthesis matrix multiplication unit 1 is as follows:
Figure BDA0001692055860000112
operation result Lv＝[l0,l1,l2,l3]TFurther output to the complex domain inverse multiplication unit;
the data bit width of the input end and the output end of the composite domain multiplication inverse operation unit is 4 bytes, and the column vector L output by the composite matrix multiplication operation unit 1 is subjected to column vector Lv＝[l0,l1,l2,l3]TEach byte in (a) performs the inverse multiplication operation on the composite domain, whereThe complex domain of (A) is optionally conjugated with GF (2)8) Complex domains with homogeneous domains, i.e. complex domain multiplication inverse unit for multiplying Lv＝[l0,l1,l2,l3]TEach byte in the complex domain multiplication inverse operation unit performs complex domain multiplication inverse operation, and the complex domain multiplication inverse operation expression performed by the complex domain multiplication inverse operation unit is as follows:
Figure BDA0001692055860000113
operation result Iv＝[i0,i1,i2,i3]TFurther output to the synthesis matrix multiplication unit 2;
the data bit width of the input end and the output end of the synthetic matrix multiplication unit 2 is 4 bytes, the data bit width of the key input port is 4 bytes, and the data vector I is processedv＝[i0,i1,i2,i3]TAnd inputting a key vector K from a key input portv＝[k0,k1,k2,k3]TAre combined into a column vector pv＝[i0,i1,i2,i3,k1,k2,k3,k4]TAnd synthesizing the matrix Lambda with the column vector pvPerforming multiplication operation to synthesize matrix Lambda from constant matrix Lambda3、λ2、λ1、
Figure BDA0001692055860000114
In combination, wherein the constant matrix λ3Is a constant matrix
Figure BDA0001692055860000115
The product of the constant matrix τ and the constant matrix δ', i.e.
Figure BDA0001692055860000116
Constant matrix lambda2Is a constant matrix
Figure BDA0001692055860000117
The product of the constant matrix τ and the constant matrix δ', i.e.
Figure BDA0001692055860000121
Constant matrix lambda1Is a constant matrix
Figure BDA0001692055860000122
The product of the constant matrix τ and the constant matrix δ', i.e.
Figure BDA0001692055860000123
Constant matrix
Figure BDA0001692055860000124
Are each GF (2)8) Domain multiplication by the constant x {03}16、×{02}16、×{01}16In the form of a matrix; the constant matrix tau is a constant matrix specified by affine operation in the AES S box; the constant matrix delta' is a mapping matrix whose role is to map elements on the complex field to GF (2)8) On the domain, the expression of the synthetic matrix Λ is specifically as follows:
Figure BDA0001692055860000125
the expression of the multiplication by the synthetic matrix multiplication unit 2 is as follows:
Figure BDA0001692055860000126
operation result Qv＝[q0,q1,q2,q3,]TFurther output to a constant addition operation unit,
a constant addition operation unit, the data bit width of the input end and the output end of which are both 4 bytes, synthesizes the vector Q output by the matrix multiplication operation unit 2v＝[q0,q1,q2,q3,]TAnd constant vector omegav＝[ω,ω,ω,ω]TAddition operation of, whereinThe number ω is a byte constant specified by affine operation in the AES S box, and the constant addition unit performs addition by the expression:
Figure BDA0001692055860000127
operation result Rv＝[r0,r1,r2,r3]TAnd output from the data output port.
The common round conversion operation unit provided by the invention combines byte replacement, row shift and column mixing and key addition operation in common round conversion operation through the synthesis matrix delta and the synthesis matrix lambda, and greatly reduces the length of a key path for realizing a common round conversion operation circuit in terms of hardware realization. In addition, the invention combines a plurality of small-scale linear operation units into large-scale linear operation through matrix combination and synthesis, thereby being beneficial to improving the optimization efficiency and reducing the realization area of realizing a common round conversion operation circuit.
The serial structure and the cycle structure are two basic structures realized by a common round conversion circuit, the common round conversion circuit with the serial structure is formed by adopting a parallel processing mode based on the common round conversion operation unit, and the common round conversion circuit with the cycle structure is formed by adopting a time-sharing multiplexing processing mode or a mode of combining time-sharing multiplexing and parallel processing.
Fig. 3 is a schematic structural diagram of a general wheel conversion circuit according to a first embodiment of the present invention, and for convenience of description, only the parts related to the first embodiment of the present invention are shown.
The ordinary round conversion circuit is used for realizing ordinary round conversion in AES encryption and comprises the following components:
4×(Nr-1) ordinary round conversion arithmetic units, wherein every 4 ordinary round conversion arithmetic units are connected in parallel to form an ordinary round conversion module, (N)r-1) the ordinary round conversion modules are connected in series to form an ordinary round conversion circuit, and each ordinary round conversion module is used for completing one ordinary round conversion operation, namely completing one encryption operation of 128-bit (16-byte) data.
Fig. 4 is a schematic structural diagram of a general wheel conversion circuit according to a second embodiment of the present invention, and only the parts related to the second embodiment of the present invention are shown for convenience of description.
The ordinary round conversion circuit is used for realizing ordinary round conversion in AES encryption and comprises the following components:
an ordinary round conversion operation unit, and a method for circulating 4 × (N)r-1) a loop feedback circuit of said ordinary round transform arithmetic unit;
the circular feedback circuit consists of an alternative selector, a register 1 and a register 2, the data bit widths of the register 1 and the register 2 are both 16 bytes, the input end of the register 1 is connected with the output end of the selector, the output end of the register 1 is connected with the input end of the register 2, the output end of the register 2 is connected with the data input end of a common round conversion operation unit, the data output end of the common round conversion operation unit is connected with one input end of the selector, the other input end of the selector is connected with the output end of a first round conversion circuit, and the output end of the common round conversion operation unit is connected with the input end of a last round conversion circuit;
the data output end of the common round conversion arithmetic unit respectively outputs the operation result after each cycle to a selector and a last round conversion circuit, and the selector outputs the first 4 (N)r-2) feeding back the operation result to the register 1, the normal round conversion unit completes 4 bytes of normal round conversion operation each time, the normal round conversion unit completes one round of complete AES normal round conversion operation through four cycles of the cycle feedback circuit, the data of the register 1 after one round of AES normal round conversion operation is input to the register 2, the register 2 outputs four bytes each time to be used as the input data of the normal round conversion operation unit for the next normal round conversion operation, and 4 (N) times of normal round conversion operation are carried out in totalr-1) the second ordinary round of transformation operation, the last round of transformation circuit will be the (4N) th roundr-7)～(4Nr-4) operation result, i.e. (N) thrAnd-1) performing last round conversion by using the result of the round ordinary round conversion operation as input data of a last round conversion circuit.
Fig. 5 is a schematic structural diagram of a general wheel conversion circuit according to a third embodiment of the present invention, and for convenience of description, only relevant portions of the third embodiment of the present invention are shown.
The ordinary round conversion circuit is used for realizing ordinary round conversion in AES encryption and comprises the following components:
a common wheel conversion module formed by two common wheel conversion operation units connected in parallel, and a circulation feedback circuit for carrying out 2 (N) on the common wheel conversion moduler-1) a cycle;
the circular feedback circuit consists of a selector, a register 1 and a register 2, the data bit widths of the register 1 and the register 2 are both 16 bytes, wherein the input end of the register 1 is connected with the output end of the selector, the output end of the register 1 is connected with the input end of the register 2, the output end of the register 2 is connected with the data input end of the common wheel conversion module, one input end of the selector is connected with the output end of the first wheel conversion circuit, the other input end of the selector is connected with the output end of the common wheel conversion module, and the output end of the common wheel conversion module is also connected with the input end of the last wheel conversion circuit;
the output end of the common round conversion operation module respectively outputs the operation results of the two common round conversion operation units to a selector and a last round conversion circuit, and the selector outputs the first 2 (N)r-2) the result of the sub-operation is fed back to the register 1. The common round conversion module finishes 8-byte common round conversion operation each time, the common round conversion module finishes one round of complete AES common round conversion operation through two cycles of the cycle feedback circuit, after one round of AES common round conversion operation is finished, the data of the register 1 is input into the register 2, the register 2 outputs two groups of 4-byte data each time, the two groups of 4-byte data serve as input data of the common round conversion operation module and are respectively input into the data input ends of the two common round conversion operation units, the next common round conversion operation is carried out, and 2 (N) is carried out in totalr-1) cycle, last round of conversion circuit will (2N)r-3)～(2Nr-2) the result of the operation of the (N) th timerAnd-1) performing last round conversion by using the result of the round ordinary round conversion operation as input data of a last round conversion circuit.
Fig. 6 is a schematic structural diagram of a general wheel conversion circuit according to a fourth embodiment of the present invention, and for convenience of description, only relevant portions of the fourth embodiment of the present invention are shown.
The ordinary round conversion circuit is used for realizing the ordinary round conversion of AES encryption and comprises the following components:
a common wheel conversion module formed by four common wheel conversion operation units connected in parallel, and a circulation feedback circuit for carrying out (N) on the common wheel conversion moduler-1) a cycle;
the circular feedback circuit is composed of a selector and a register, the data bit width of the register is 16 bytes, the output end of the register is connected with the input end of the common round conversion module, the input end of the register is connected with the output end of the selector, one input end of the selector is connected with the output end of the first round conversion circuit, the other input end of the selector is connected with the output end of the common round conversion module, and the output end of the common round conversion operation module is further connected with the input end of the last round conversion circuit.
The common round conversion module completes 16 bytes of common round conversion operation each time, and completes one round of complete common round conversion operation through one cycle of the cycle feedback circuit;
the output end of the common wheel conversion module respectively outputs the operation results of the four common wheel conversion operation units to a selector and a last wheel conversion circuit, and the selector outputs the result of the previous (N)r-2) result of sub-operation RvFeeding back to the input end of the ordinary round conversion module, inputting the data input ends of the four ordinary round conversion operation units respectively, and performing the next round of ordinary round conversion operation (N)r-1) normal round conversion, the last round conversion circuit will be the (N) th roundr-1) result of sub-operation RvThe last round conversion operation is performed as input data of the last round conversion circuit.
Compared with the common wheel conversion circuit with the serial structure, the common wheel conversion circuit with the circulating structure has the advantages that the circuit area is greatly reduced, so that the common wheel conversion circuit is suitable for a data processing circuit with limited area; however, the common wheel conversion circuit with the serial structure adopts the pipeline technology, so that the circuit processing speed can be greatly improved, and the circuit is suitable for a high-speed data processing circuit, so that the structure of the common wheel conversion circuit can be designed according to actual requirements;
in addition, based on the ordinary round conversion circuit formed by the ordinary round conversion operation unit, the ordinary round conversion operation unit combines the complex domain mapping operation, the affine operation, the column mixing operation and the key addition operation in the AES cryptographic algorithm through the synthesis matrix delta and the synthesis matrix lambda, and the key path length of the circuit can be greatly reduced based on the ordinary round conversion circuit formed by the ordinary round conversion operation unit in terms of hardware implementation. The public item eliminating algorithm is the most effective circuit optimization method of the linear operation unit, and researches show that the larger the circuit scale is, the higher the circuit efficiency is, so that the invention combines a plurality of small-scale linear operation units into large-scale linear operation through matrix combination and synthesis, is beneficial to improving the circuit optimization efficiency, and reduces the realization area of a common round conversion circuit.
In an embodiment of the present invention, there is further provided an AES encryption circuit, including: the first round conversion circuit, the common round encryption circuit and the last round conversion circuit are sequentially connected in series, the common round conversion circuit adopts the common round conversion circuits provided by the first embodiment, the second embodiment, the third embodiment and the fourth embodiment, and the first round conversion circuit and the last round conversion circuit both adopt the existing structures.
The AES encryption circuit provided by the embodiment of the invention is formed based on the common round conversion circuit, the common round conversion circuit is formed based on the common round conversion operation unit, and the common round conversion operation unit combines the composite domain mapping operation, the affine operation, the column mixing operation and the key addition operation in the AES cipher algorithm through the synthesis matrix delta and the synthesis matrix lambda, so that the AES encryption circuit greatly reduces the length of a key path of the circuit in terms of hardware realization. The public item eliminating algorithm is the most effective circuit optimization method of the linear operation unit, and researches show that the larger the circuit scale is, the higher the circuit efficiency is, so that the invention combines a plurality of small-scale linear operation units into large-scale linear operation through matrix combination and synthesis, thereby being beneficial to improving the circuit optimization efficiency and reducing the realization area of the AES encryption circuit.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (6)

1.一种普通轮变换运算单元，用于AES加密，其特征在于，所述普通轮变换运算单元包括：1. a common round transformation operation unit, is used for AES encryption, it is characterized in that, described common round transformation operation unit comprises: 输入端与数据输入端口连接的合成矩阵乘法运算单元1；输入端与合成矩阵乘法运算单元1输出端连接的复合域乘法逆运算单元；输入端与复合域乘法逆运算单元输出端、密钥输入端口连接的合成矩阵乘法运算单元2；输入端与合成矩阵乘法运算单元2输出端连接的常数加运算单元，常数加运算单元输出端与数据输出端口相连接，其中，A composite matrix multiplication operation unit 1 whose input terminal is connected to a data input port; a composite domain multiplication and inverse operation unit whose input terminal is connected to the output end of the composite matrix multiplication operation unit 1; The synthetic matrix multiplying operation unit 2 connected by the port; the constant addition operation unit whose input end is connected with the output end of the synthetic matrix multiplying operation unit 2, and the output end of the constant addition operation unit is connected with the data output port, wherein, 合成矩阵乘法运算单元1，从数据输入端口输入四个字节的列向量Dv＝[d0,d1,d2,d3]T，将合成矩阵Δ与列向量Dv进行乘法运算，将乘法运算后的矩阵Lv＝[l0,l1,l2,l3]T输出到复合域乘法逆运算单元，其中，合成矩阵Δ的表达式如下：The synthetic matrix multiplication unit 1 inputs a four-byte column vector D v =[d 0 , d 1 , d 2 , d 3 ] T from the data input port, and multiplies the synthetic matrix Δ and the column vector D v , The multiplied matrix L v =[l 0 ,l 1 ,l 2 ,l 3 ] T is output to the composite field multiplication and inversion operation unit, wherein the expression of the composite matrix Δ is as follows:
Figure FDA0002791752240000011
Figure FDA0002791752240000011
 复合域乘法逆运算单元，将Lv＝[l0,l1,l2,l3]T中的每个字节进行复合域乘法逆运算，并将复合域乘法逆运算后的矩阵Iv＝[i0,i1,i2,i3]T输出到合成矩阵乘法运算单元2，其中，常数矩阵δ为映射矩阵，其作用是将GF(28)域上的元素映射到复合域上；The composite field multiplication and inversion operation unit, performs the composite field multiplication and inversion operation on each byte in L v =[l 0 ,l 1 ,l 2 ,l 3 ] T , and performs the composite field multiplication and inversion operation on the matrix I v =[i 0 , i 1 , i 2 , i 3 ] T is output to the composite matrix multiplication unit 2, where the constant matrix δ is a mapping matrix, and its function is to map the elements on the GF(2 8 ) field to the composite field superior; 合成矩阵乘法运算单元2，将矩阵Iv＝[i0,i1,i2,i3]T及从密钥输入端口输入的密钥向量Kv＝[k0,k1,k2,k3]T组合成一个列向量pv＝[i0,i1,i2,i3,k1,k2,k3,k4]T，将合成矩阵Λ与列向量pv进行乘法运算，将乘法运算后的矩阵Qv＝[q0,q1,q2,q3]T输出到常数加运算单元，其中，合成矩阵Λ表示如下：The synthetic matrix multiplication unit 2 combines the matrix I v =[i 0 ,i 1 ,i 2 ,i 3 ] T and the key vector K v =[k 0 ,k 1 ,k 2 , which is input from the key input port, k 3 ] T is combined into a column vector p v =[i 0 ,i 1 ,i 2 ,i 3 ,k 1 ,k 2 ,k 3 ,k 4 ] T , and the resultant matrix Λ is multiplied by the column vector p v operation, the multiplication matrix Q v =[q 0 , q 1 , q 2 , q 3 ] T is output to the constant addition operation unit, wherein the composite matrix Λ is expressed as follows:
Figure FDA0002791752240000021
Figure FDA0002791752240000021
 常数加运算单元，将矩阵Qv＝[q0,q1,q2,q3]T与常数向量Ωv＝[ω,ω,ω,ω]T相加运算，相加运算后的矩阵Rv＝[r0,r1,r2,r3]T从数据输出端口输出，其中，常数ω为AES S盒中仿射运算所指定的字节常数，其中常数矩阵λ3为常数矩阵
Figure FDA0002791752240000022
常数矩阵τ和常数矩阵δ′的乘积，即
Figure FDA0002791752240000023
常数矩阵λ2为常数矩阵
Figure FDA0002791752240000024
常数矩阵τ和常数矩阵δ′的乘积，即
Figure FDA0002791752240000025
常数矩阵λ1为常数矩阵
Figure FDA0002791752240000026
常数矩阵τ和常数矩阵δ′的乘积，即
Figure FDA0002791752240000027
常数矩阵
Figure FDA0002791752240000028
分别为GF(28)域上乘常数×{03}16、×{02}16、×{01}16的矩阵形式；常数矩阵τ为AES S盒中仿射运算所指定的常数矩阵；常数矩阵δ′为映射矩阵，其作用是将复合域上的元素映射到GF(28)域上；The constant addition operation unit, adds the matrix Q v =[q 0 ,q 1 ,q 2 ,q 3 ] T and the constant vector Ω v =[ω,ω,ω,ω] T , and the matrix after the addition operation R v =[r 0 ,r 1 ,r 2 ,r 3 ] T is output from the data output port, where the constant ω is the byte constant specified by the affine operation in the AES S-box, where the constant matrix λ 3 is the constant matrix
Figure FDA0002791752240000022
The product of the constant matrix τ and the constant matrix δ′, that is
Figure FDA0002791752240000023
The constant matrix λ 2 is a constant matrix
Figure FDA0002791752240000024
The product of the constant matrix τ and the constant matrix δ′, that is
Figure FDA0002791752240000025
The constant matrix λ 1 is a constant matrix
Figure FDA0002791752240000026
The product of the constant matrix τ and the constant matrix δ′, that is
Figure FDA0002791752240000027
constant matrix
Figure FDA0002791752240000028
are the matrix forms of the multiplication constants ×{03} 16 , ×{02} 16 , and ×{01} 16 in the GF(2 8 ) field respectively; the constant matrix τ is the constant matrix specified by the affine operation in the AES S box; the constant matrix δ' is the mapping matrix, whose function is to map the elements on the composite field to the GF(2 8 ) field; 合成矩阵乘法运算单元1、复合域乘法逆运算单元、合成矩阵乘法运算单元2、及常数加运算单元的数据输入端及数据输出端的数据位宽均为4个字节，密钥输入端口的数据位宽均为4个字节。The data bit width of the data input end and the data output end of the composite matrix multiplication unit 1, the composite field multiplication inversion unit, the composite matrix multiplication unit 2, and the constant addition unit are 4 bytes, and the data of the key input port is 4 bytes. The bit width is 4 bytes. 2.一种用于AES加密的普通轮变换电路，其特征在于，所述普通轮变换电路由4×(Nr-1)个如权利要求1所述的普通轮变换运算单元组成，Nr为轮变换数量；2. a common rotary conversion circuit for AES encryption, is characterized in that, described common rotary conversion circuit is made up of 4*(N r -1) common rotary conversion arithmetic units as claimed in claim 1, N r is the number of rotations; 其中，每4个所述普通轮变换运算单元并联组成一个用于完成一次普通轮变换运算的普通轮变换模块，(Nr-1)个普通轮变换模块串联组成普通轮变换电路。Wherein, every 4 of the common wheel conversion operation units are connected in parallel to form a common wheel conversion module for completing one common wheel conversion operation, and (N r -1) common wheel conversion modules are connected in series to form a common wheel conversion circuit. 3.一种用于AES加密的普通轮变换电路，其特征在于，所述普通轮变换电路包括：一个如权利要求1所述的普通轮变换运算单元、及用于循环4×(Nr-1)次所述普通轮变换运算单元的循环反馈电路，Nr为轮变换数量；3. A common round conversion circuit for AES encryption, characterized in that the common round conversion circuit comprises: an ordinary round conversion arithmetic unit as claimed in claim 1, and a common round conversion operation unit for cyclic 4×(N r − 1) the loop feedback circuit of the ordinary round transformation arithmetic unit described in times, N r is the round transformation quantity; 其中，循环反馈电路由选择器、寄存器1及寄存器2组成，寄存器1输入端与选择器的输出端连接，寄存器1的输出端与寄存器2的输入端相连接，寄存器2的输出端与普通轮变换运算单元输入端连接，普通轮变换运算单元的输出端与选择器的一输入端连接，选择器的另一输入端与首轮变换电路的输出端连接，普通轮变换运算单元的输出端连接还与末轮变换电路的输入端连接；Among them, the loop feedback circuit consists of selector, register 1 and register 2. The input end of register 1 is connected to the output end of the selector, the output end of register 1 is connected to the input end of register 2, and the output end of register 2 is connected to the common wheel The input end of the transformation operation unit is connected, the output end of the ordinary round transformation operation unit is connected with an input end of the selector, the other input end of the selector is connected with the output end of the first round transformation circuit, and the output end of the ordinary round transformation operation unit is connected It is also connected with the input end of the final wheel conversion circuit; 所述寄存器1及所述寄存器2的数据位宽均为16字节。The data bit widths of the register 1 and the register 2 are both 16 bytes. 4.一种用于AES加密的普通轮变换电路，其特征在于，所述普通轮变电路包括：由两个如权利要求1所述的普通轮变换运算单元并联组成的普通轮变换模块，及循环反馈电路，所述循环反馈电路用于对普通轮变换模块进行2(Nr-1)次循环，Nr为轮变换数量；4. a common rotary conversion circuit for AES encryption, is characterized in that, described common rotary conversion circuit comprises: the common rotary conversion module that is formed in parallel by two common rotary conversion arithmetic units as claimed in claim 1, and A loop feedback circuit, the loop feedback circuit is used to perform 2 (N r -1) cycles on the common round transformation module, where N r is the number of round transformations; 其中，循环反馈电路由选择器、寄存器1及寄存器2组成，寄存器1的输入端与选择器的输出端连接，寄存器1的输出端与寄存器2的输入端连接，寄存器2的输出端与普通轮变换模块的输入端连接，首轮变换电路的输出端与选择器的一输入端连接，选择器的另一输入端与普通轮变换模块的输出端连接，普通轮变换模块的输出端还与末轮变换电路的输入端连接；Among them, the loop feedback circuit consists of a selector, register 1 and register 2. The input end of register 1 is connected to the output end of the selector, the output end of register 1 is connected to the input end of register 2, and the output end of register 2 is connected to the common wheel. The input end of the conversion module is connected, the output end of the first round conversion circuit is connected with an input end of the selector, the other input end of the selector is connected with the output end of the common wheel conversion module, and the output end of the common wheel conversion module is also connected with the end. The input terminal of the wheel conversion circuit is connected; 所述寄存器1及所述寄存器2的数据位宽均为16字节。The data bit widths of the register 1 and the register 2 are both 16 bytes. 5.一种用于AES加密的普通轮变换电路，其特征在于，所述普通轮变电路包括：由四个如权利要求1所述的普通轮变换运算单元并联组成的普通轮变换模块，及循环反馈电路，所述循环反馈电路用于对普通轮变换模块进行(Nr-1)次循环，Nr为轮变换数；5. a common rotary conversion circuit for AES encryption, is characterized in that, described common rotary conversion circuit comprises: the common rotary conversion module that is formed in parallel by four common rotary conversion arithmetic units as claimed in claim 1, and A loop feedback circuit, the loop feedback circuit is used to perform (N r -1) cycles on the common round transformation module, where N r is the round transformation number; 其中，所述循环反馈电路由选择器及寄存器组成，所述寄存器的输出端与普通轮变换模块的输入端连接，所述寄存器输入端与选择器的输出端连接，所述选择器的一输入端与首轮变换电路的输出端连接，另一输入端与对应的普通轮变换模块的输出端连接，普通轮变换运算模块的输出端还与末轮变换电路的输入端连接；Wherein, the loop feedback circuit is composed of a selector and a register, the output end of the register is connected with the input end of the common rotary module, the input end of the register is connected with the output end of the selector, an input end of the selector The terminal is connected with the output terminal of the first round conversion circuit, the other input terminal is connected with the output terminal of the corresponding ordinary round conversion module, and the output terminal of the ordinary round conversion operation module is also connected with the input terminal of the last round conversion circuit; 所述寄存器的数据位宽为16字节。The data bit width of the register is 16 bytes. 6.一种AES加密电路，其特征在于，所述AES加密电路包括：6. an AES encryption circuit, is characterized in that, described AES encryption circuit comprises: 依次串联连接的首轮变换电路、如权利要求2至5任一权利要求所述普通轮加密电路、及末轮变换电路。The first round conversion circuit, the ordinary round encryption circuit according to any one of claims 2 to 5, and the last round conversion circuit connected in series in sequence.
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