CN108932388A - A kind of mould 2 based on quantum superposition statenSubtracter design method - Google Patents

Abstract

A kind of mould 2 based on quantum superposition stateⁿSubtracter design method, the method realizes the design method of quantum half-subtracter and restorer, quantum full subtracter and restorer using the controlled door of basic quantum, and constitutes n quantum moulds 2 by quantum half-subtracter, quantum full subtracter and restorerⁿThe design method of subtracter；Finally utilize designed mould 2ⁿSubtracter realizes the mould 2 based on quantum superposition stateⁿSubtraction.The present invention solves the quantum mould 2 of quantum superposition stateⁿSubtraction problem devises the quantum mould 2 based on quantum superposition stateⁿSubtracter.The present invention embodies quantum information processing in the high efficiency of signal processing: 14n-13 basic operation only being needed to achieve that 2^mA n integer mould 2ⁿSubtraction, and realize that corresponding add operation needs O (n2 with classic computer^m) basic operation.The quantum mould 2 of Figure of abstract n quantum bit of the present inventionⁿThe quantum wire figure of subtracter.

Description

A Design Method of Modular 2n Subtractor Based on Quantum Superposition State

technical field

The invention relates to a design method of a modulo ²ⁿ subtractor based on quantum superposition state, and belongs to the technical field of quantum circuit design.

Background technique

Modulo 2 ⁿ subtraction is expressed as

MS(ba)=sign(ba)×[(ba)mod 2 ⁿ ] (1)

Where a, b are n-bit positive integers. When b<a, sign(ba)=-1, and when b≥a, sign(ba)=1. (ba) mod 2 ⁿ is (ba) modulo operation on 2 ⁿ , the operation rules are as follows

In quantum computing, the information unit is represented by a qubit, which has two basic quantum states |0> and |1>, and the basic quantum state is called the ground state for short. A qubit can be a linear combination of two ground states, often called a superposition state, which can be expressed as |ψ>=a|0>+b|1>, where a and b are two complex numbers.

Tensor product is a method of combining small vector spaces to form a larger vector space, using the symbol express. For two ground states |u> and |v>, their tensor product Commonly used abbreviations |uv>, |u>|v> or |u, v>, for example, for the ground state |0> and |1>, their tensor product can be expressed as:

For n tensor products of matrix U Can be abbreviated as For the n times tensor product of quantum state |u> can also be abbreviated as

A quantum circuit can be composed of a sequence of qubit gates. In the representation diagram of a quantum circuit, each line represents the connection of the quantum circuit, and the execution order of the quantum circuit is from left to right. The qubit gate can conveniently represent X (NOT gate) in matrix form. V, V ⁺ and unit gate are three commonly used single-qubit gates. Their matrix representations are:

where i is the imaginary unit.

The most important multi-qubit gate is the controlled U-gate, which consists of a control qubit and a target qubit, represented by a black dot when the control bit is 1, and a white dot when the control bit is 0. When U=X, V, V ⁺ , the controlled U gates are respectively called controlled NOT gates, controlled V gates, and controlled V ⁺ gates, and their symbols are shown in Figure 1.

An integer less than 2 ⁿ can be represented by n qubits: |b _n-1 b _n-2 ...b ₀ >, where b _h ∈ {0,1}, h=0,...,n-1 .

Further, the n+m qubit state

A column vector of size 2 ^m can be stored:

Wherein b(j) is an n-bit integer, j=0,...,2 ^m −1, and both n and m are positive integers.

The performance index of a quantum circuit is the complexity of the circuit. The complexity of the circuit refers to the total number of controlled NOT gates, controlled V gates, and controlled V ⁺ gates in the circuit.

Contents of the invention

The object of the invention is to propose a modulo 2 ⁿ subtractor design method based on the quantum superposition state in order to solve the quantum subtraction operation problem of the quantum superposition state.

The technical scheme realized by the present invention is as follows, a method for designing a modulus ²ⁿ subtractor based on quantum superposition state, said method utilizes basic quantum controlled gates to realize the design of quantum half subtractor and resetter, quantum full subtractor and resetter method, and the design method of an n-bit quantum modulus 2 ⁿ subtractor composed of quantum half subtractor, quantum full subtractor and reset device; finally, the modulo 2 ^{n subtraction operation based on the quantum superposition state is realized by using the designed modulo 2 n subtractor} . The basic quantum controlled gate includes a controlled NOT gate, a controlled V gate and a controlled quantum full adder V ⁺ gate.

The design method of described quantum half reducer and resetter is as follows:

Use four controlled gates to realize the design circuit of the quantum half reducer, represented by the symbol Q; the four controlled gates include a controlled NOT gate, two controlled V gates and a controlled V ⁺ gate; these four controlled The connection sequence of the gates is: controlled V ⁺ gate, controlled V gate, controlled NOT gate, controlled V gate.

Applying the quantum half reducer to the quantum state |c _i >|b _i >|a _i >, we get:

in is an XOR operation, c _i , b _i , a _i ∈ {0,1}, When |c _i >=|0>, it can be seen from the above formula that the quantum half subtractor implements subtraction ( _{bi -a i )} , where the first qubit output Store the borrow information of the subtraction (b _i -a _i ), the second qubit of the output What is stored is the difference of the subtraction;

In order to reset the auxiliary qubit after subtraction to the initial state, the reset device of the quantum half-subtractor is designed, which is composed of five controlled gates, represented by the symbol Q _o ; the five controlled gates include two controlled NOT gates, Two controlled V gates and one controlled V ⁺ gate; the connection sequence of these five controlled gates is: controlled V ⁺ gate, controlled V gate, controlled NOT gate, controlled V gate, controlled NOT gate .

Applying the resetter of a quantum half-machine to a quantum state get:

in is an XOR operation, c _i , b _i , a _i ∈ {0,1}, From the formula Q(|c _i >|b _i >|a _i >), it can be seen that the reset device of the quantum half reducer will reset to | _ci >;

The complexity of the quantum half reducer is 4, and the corresponding resetter is 5.

The design method of described quantum full subtractor and resetter is as follows:

Utilize six controlled gates to design the design circuit of the quantum full subtractor, the quantum full subtractor is represented by the symbol S; the six controlled gates include two controlled NOT gates, three controlled V gates and one controlled V ⁺ gate; The connection sequence of the six controlled gates is: controlled V gate, controlled NOT gate, controlled V gate, controlled NOT gate, controlled V ⁺ gate, controlled V gate.

Applying the quantum total subtractor to the quantum state |c _i >|b _i >|a _i >|c _i-1 >, we get:

in is an XOR operation, c _i , b _i , a _i , c _i-1 ∈ {0,1}, When |c _i >=|0>, it can be seen from the above formula that the quantum full subtractor realizes the subtraction (b _i -a _i -c _i-1 ), in which the output of the first qubit Store the borrow information of the subtraction (b _i -a _i -c _i-1 ), the second qubit of the output What is stored is the difference of the subtraction;

In order to reset the auxiliary qubit after the subtraction to the initial state, the resetter of the quantum full subtractor is made up of eight controlled gates, represented by symbol S1 _; the eight controlled gates include four controlled NOT gates, three A controlled V gate and a controlled V ⁺ gate; the connection sequence of these eight controlled gates is: controlled V gate, controlled NOT gate, controlled V gate, controlled NOT gate, controlled V ⁺ gate, Controlled V gate, controlled NOT gate, controlled NOT gate.

Applying the resetter of a quantum full subtractor to a quantum state get:

in is an XOR operation, c _i , b _i , a _i , c _i-1 ∈ {0,1}, From the formula (6), it can be seen that the reset device of the quantum full subtractor will be reset to | _ci >;

The complexity of the quantum full subtractor is 6, and the corresponding reset device is 8.

The design method of the quantum modulus ²ⁿ subtractor of described n qubit is as follows:

Utilize the quantum half subtractor, the quantum full subtractor and the corresponding resetter to design the circuit of the modulus 2 ⁿ subtractor of n qubits, and the modulus 2 ⁿ subtractor of n qubits is represented by the symbol M _U ;

The modulo 2 ⁿ subtractor of n qubits consists of (n-1) quantum full subtractors, resets of (n-2) quantum full subtractors, 1 quantum half subtractor and 1 reset of quantum half subtractors device, which implements the modulo 2 ⁿ subtraction of two n-bit integers;

Suppose n-bit integers a and b are stored in the ground state of two n-qubits as follows:

Among them, a _n-1 a _n-2 ... a ₀ and b _n-1 b _n-2 ... b ₀ are the binary representations of integers a and b respectively, a _h , b _h ∈ {0,1}, h=0 ,...,n-1;

Quantum ground state with n qubits added As the auxiliary bit of the subtraction operation, and arranged in order to get |0b _{n- 1} a _n-1 0b _n-2 a _n-2 ... 0b ₀ a ₀ > as input; apply the modulo 2 ⁿ subtractor to |0b _n-1 a _n-1 0b _n-2 a _n-2 …0b ₀ a ₀ >, get:

M _U |0b _n-1 a _n-1 0b _n-2 a _n-2 …0b ₀ a ₀ >＝|d _n d _n-1 a _n-1 0d _n-2 a _n-2 …0d ₀ a ₀ >

Where d _n represents the sign bit, d _n =0 represents a positive number, d _n =1 represents a negative number, d _n-1 d _n-2 ... d ₀ is the binary representation of an integer [(ba) mod 2 ⁿ ], d _h ∈ {0,1}, h=0,...,n-1.

It can be seen from the above formula that the modulo ²ⁿ subtractor realizes the following modulo ²ⁿ subtraction operation:

The complexity of realizing the quantum modulo 2 ⁿ subtraction of an n-bit integer is 6(n-1)+8(n-2)+4+5=14n-13, n≥2.

The implementation method of the modulus ²ⁿ subtractor operation based on the quantum superposition state is as follows:

column vector of 2 ^m elements Stored in the quantum superposition state of (n+m) qubits as follows

Wherein b(j) is an n-bit integer, j=0,...,2 ^m -1, n and m are both positive integers;

The modulo ²ⁿ subtractor M _U and Tensor operations get new quantum operations where the symbol is a tensor operation symbol. Will applied to the following formula,

get:

where a _n-1 a _n-2 ...a ₀ , b(j) _n-1 b(j) _n-2 ...b(j) ₀ and d(j) _n-1 d(j) _{n -2} ...d(j) ₀ is the binary representation of integers a, b(j) and d(j) respectively; d(j)=(b(j)-a)mod 2 ⁿ ; a _h , b( j) _h ,d(j) _h ∈{0,1}; h=0,1,...,n-1,n,m are integers; d(j) _n represents the sign bit of d(j)-a ; d(j) _n =0 represents a positive number; d(j) _n =1 represents a negative number;

It can be seen from the above formula, Realize the following modulo 2 ⁿ subtraction operation:

in, That is, the following subtraction operation is realized:

The modulo ²ⁿ subtraction operation is composed of an n qubit quantum modulo ²ⁿ subtractor and m qubit lines.

The modulo ²ⁿ subtraction operation is used for the n-1 qubit ground state of the auxiliary operation The quantum state |ψ _(ab) >|a> stored in the modulus 2 ⁿ subtraction operation will not be entangled, so it can be removed after the modulo 2 ⁿ subtraction operation.

The circuit complexity of the modulo 2 ⁿ subtraction operation is 14n-13, and the modulo 2 ⁿ subtraction operation of 2 ^m n-bit integers can be realized in parallel.

The beneficial effect of the present invention is that the present invention solves the problem of "quantum modulus 2 ⁿ subtraction in quantum superposition state", and designs a quantum modulus 2 ⁿ subtractor based on quantum superposition state. The present invention embodies the high efficiency of quantum information processing in signal processing: only 14n-13 basic operations can realize 2 ^m n-bit integer modulo 2 ⁿ subtraction operations, while using a classical computer to realize the corresponding addition operation requires O(n2 ^m ) Basic operations. Another advantage of the present invention is that the resetter is designed so that the auxiliary quantum ground state participating in the operation and the quantum state storing the addition operation result will not be entangled together.

Description of drawings

Fig. 1 is the title and symbol representation figure of qubit gate of the present invention;

Fig. 2 is the quantum realization circuit diagram of quantum half reducer of the present invention;

Fig. 3 is the sketch map of the quantum realization circuit of quantum half reducer of the present invention;

Fig. 4 is the quantum realization circuit diagram of the reset device of quantum half reducer of the present invention;

Fig. 5 is the quantum realization circuit diagram of the reset device of quantum half reducer of the present invention;

Fig. 6 is the quantum realization circuit diagram of quantum full subtractor of the present invention;

Fig. 7 is the quantum realization circuit diagram of quantum full subtractor of the present invention;

Fig. 8 is the quantum realization circuit diagram of the reset device of quantum full subtractor of the present invention;

Fig. 9 is the quantum realization circuit diagram of the reset device of quantum full subtractor of the present invention;

Fig. 10 is the quantum circuit diagram of the quantum modulus ²ⁿ subtractor of n qubit of the present invention;

Fig. 11 is the quantum circuit diagram of the quantum modulus ²ⁿ subtractor of n qubits of the present invention;

Fig. 12 is the quantum circuit diagram of the modulus ²ⁿ subtraction operation based on the quantum superposition state of the present invention;

Fig. 13 is a quantum implementation circuit diagram of an example of a modulo ²ⁿ subtraction operation based on quantum superposition states in the present invention.

Detailed ways

The specific embodiment of the present invention is as follows:

In this embodiment, a method for designing a modulus ²ⁿ subtractor based on a quantum superposition state, the method utilizes a basic quantum controlled gate to realize the design method of a quantum half subtractor and a resetter, a quantum full subtractor and a resetter, and the quantum The design method of the n-bit quantum modulo 2 ⁿ subtractor composed of the half subtractor, the quantum full subtractor and the reset device; finally, the modulo 2 ^{n subtraction operation based on the quantum superposition state is realized by using the designed modulo 2 n subtractor} .

1. The design method of quantum half reducer and reset device in this embodiment

In this embodiment, four controlled gates are used to realize the design circuit of the quantum half reducer as shown in FIG. The four controlled gates include a controlled NOT gate, two controlled V gates and a controlled V ⁺ gate.

Applying the quantum half reducer to the quantum state |c _i >|b _i >|a _i >, we get

in is an XOR operation, c _i , b _i , a _i ∈ {0,1}, When |c _i >=|0>, it can be seen from the formula (3) that the quantum half subtractor implements the subtraction ( _{bi -a i )} , where the first qubit output Store the borrow information of the subtraction (b _i -a _i ), the second qubit of the output What is stored is the difference of the subtraction.

In order to reset the auxiliary qubit after the subtraction to the initial state, design the reset device of the quantum half subtractor as shown in Figure 4, which consists of 5 controlled gates, including two controlled NOT gates and two controlled V gates And a controlled V+ gate, its simplified diagram is shown in Figure 5, represented by the symbol Qo.

Applying the resetter of a quantum half-machine to a quantum state get

in is an XOR operation, c _i , b _i , a _i ∈ {0,1}, From the formula (3), it can be seen that the reset device of the quantum half reducer will be Reset to | _ci >.

Analyzing the quantum circuit in Fig. 2 and Fig. 4, it can be obtained that the complexity of the quantum half reducer is 4, and the corresponding resetter is 5.

2. The design method of quantum total subtractor and reset device in this embodiment

In this embodiment, six controlled gates are used to realize the design circuit of the quantum total subtractor as shown in FIG. 6 . The six controlled gates include two controlled NOT gates, three controlled V gates and one controlled V ⁺ gate.

Applying the quantum total subtractor to the quantum state |c _i >|b _i >|a _i >|c _i-1 >, we get

in is an XOR operation, c _i , b _i , a _i , c _i-1 ∈ {0,1}, When |c _i >=|0>, it can be seen from the formula (5) that the quantum total subtractor realizes the subtraction (b _i -a _i -c _i-1 ),

where the output of the first qubit Store the borrow information of the subtraction (b _i -a _i -c _i-1 ), the second qubit of the output What is stored is the difference of the subtraction.

In order to reset the auxiliary qubit after the subtraction to the initial state, the reset device of the quantum full subtractor shown in Figure 8 is designed, which consists of 8 controlled gates, including four controlled NOT gates and three controlled V gates and a controlled V ⁺ gate, the simplified diagram of which is shown in Figure ₉ , denoted by the symbol S1.

Applying the resetter of a quantum full subtractor to a quantum state get

in is an XOR operation, c _i , b _i , a _i , c _i-1 ∈ {0,1}, From the formula (6), it can be seen that the reset device of the quantum full subtractor will be Reset to | _ci >.

Analyzing the quantum circuits in Figure 6 and Figure 8, it can be obtained that the complexity of the quantum full subtractor is 6, and the corresponding reset device is 8.

3. The design method of the quantum modulus ²ⁿ subtractor of n qubits in this embodiment

In this embodiment, the quantum half subtractor, the quantum full subtractor and the corresponding reset device are used to realize the design circuit of the modulo 2 ⁿ subtractor of n qubits as shown in FIG. 10 , which is represented by the symbol M _U . The modulo 2 ⁿ subtractor of n qubits consists of (n-1) quantum full subtractors, resets of (n-2) quantum full subtractors, 1 quantum half subtractor and 1 reset of quantum half subtractors device, which implements the modulo 2 ⁿ subtraction of two n-bit integers.

Suppose n-bit integers a and b are stored in the ground state of two n-qubits as follows:

where a _n-1 a _n-2 ... a ₀ and b _n-1 b _n-2 ... b ₀ are the binary representations of integers a and b respectively, a _h , b _h ∈ {0,1}, h=0, ..., n-1.

Quantum ground state with n qubits added It is the auxiliary bit of the subtraction operation, and the sequence is arranged to get |0b _{n- 1} a _n-1 0b _n-2 a _n-2 ... 0b ₀ a ₀ > as input. Applying the modulo 2 ⁿ subtractor to |0b _n-1 a _n-1 0b _n-2 a _n-2 ... 0b ₀ a ₀ > gives:

M _U |0b _n-1 a _n-1 0b _n-2 a _n-2 ... 0b ₀ a ₀ >＝|d _n d _n-1 a _n-1 0d _n-2 a _n-2 ... 0d ₀ a ₀ > (8)

Where d _n represents the sign bit, d _n =0 represents a positive number, d _n =1 represents a negative number, d _n-1 d _n-2 ... d ₀ is the binary representation of an integer [(ba) mod 2 ⁿ ], d _h ∈ {0,1}, h=0,...,n-1, the meaning of [(ba)mod 2 ⁿ ] is as described in formula (1).

It can be known from the formula (8) that the modulo ²ⁿ subtractor realizes the following modulo ²ⁿ subtraction operation:

Therefore, the simplified diagram of the modulo 2 ⁿ subtractor can be represented by the symbols in Fig. 11.

Analyzing the quantum circuit in Figure 10, it can be obtained that the complexity of realizing a quantum modulo 2 ⁿ subtraction of an n-bit integer is 6(n-1)+8(n-2)+4+5=14n-13, n≥ 2.

4. In this embodiment, the implementation of the modulo 2 ⁿ subtractor operation based on the quantum superposition state

From formula (2), we can see that the column vector of 2 ^m elements It can be stored in the quantum superposition state of the following (n+m) qubits:

Wherein b(j) is an n-bit integer, j=0,...,2 ^m −1, and both n and m are positive integers.

The modulo ²ⁿ subtractor M _U and Tensor operations get new quantum operations where the symbol is a tensor operation symbol.

Will applicable to

get

where a _n-1 a _n-2 ... a ₀ , b(j) _n-1 b(j) _n-2 ... b(j) ₀ and d(j) _n-1 d(j) _n-2 ...d(j) ₀ is the binary representation of the integers a, b(j) and d(j) respectively, d(j)=(b(j)-a)mod 2 ⁿ ,a _h ,b(j) _h ,d(j) _h ∈{0,1}, h=0,1,...,n-1,n, m is an integer, d(j) _n represents the sign bit of d(j)-a, d (j) _n =0 indicates a positive number, and d(j) _n =1 indicates a negative number.

From formula (10), we can see that Realize the following modulo 2 ⁿ subtraction operation:

in That is, the following addition operation is realized:

Here, MS(), sign(), mod 2 ⁿ are as shown in formula (1).

It can be seen from formula (10) that designing the quantum circuit as shown in Figure 12 can realize the modulo 2 ⁿ subtraction operation in formula (12), which consists of a quantum modulo 2 ⁿ subtractor of n qubits and lines of m qubits.

It can be seen from formula (11) that the ground state of n-1 qubits used for auxiliary operations The quantum state |ψ _(ab) >|a> stored in the modulus 2 ⁿ subtraction operation will not be entangled, so it can be removed after the modulo 2 ⁿ subtraction operation.

Analyzing the quantum circuit in Fig. 12, it can be obtained that the circuit complexity of the modulus 2 ⁿ subtraction operation based on the quantum superposition state is 14n-13, and it can realize 2 ^m n-bit integer modulo 2 ⁿ subtraction operations in parallel, which fully embodies the present invention High efficiency for modulo ²ⁿ subtraction circuits is achieved.

The concrete implementation of the present invention is as follows:

It can be known from formula (2) that when m=3, n=3, a 2 ³ ×1 integer vector [0 1 2 3 4 5 6 7] ^T can be stored in the following quantum state:

where b(j)=j, j=0,1,...,7.

Design the quantum circuit shown in Figure 13 to realize the following 8 modulus 2 ³ subtraction operations:

MS([0 1 2 3 4 5 6 7] ^T -5)＝[-3 -4 -5 -6 -7 0 1 2] ^T (14)

where [] ^T is the transpose of the matrix.

The quantum circuit in the virtual frame of Fig. 13 is a quantum adder of 3 qubits, which consists of 2 quantum full adders, a reset device of a quantum full adder, a quantum half adder and a reset of a quantum half adder Therefore, the complexity of the circuit is 29, that is, a 3-digit modulo 2 ³ subtraction can be realized by 29 quantum basic operations. It can be seen from formula (11) that the quantum circuit in Figure 13 implements the following modulo 2 ³ subtraction operation:

in:

It can be seen from formula (15) that the quantum circuit in Figure 13 implements the 8 modulo 2 ³ subtraction operations in formula (14), and assists the qubit will not be entangled with |ψ _(b-5) >.

Since applying the 3-qubit quantum modulus 2 ³ subtractor to the quantum superposition state does not need to add a new quantum gate, because the complexity of the quantum circuit in Fig. 13 is also 29.

Claims (8)

1. Mode 2 based on quantum superposition stateⁿThe design method of the subtracter is characterized in that the method utilizes a quantum controlled gate to realize the design method of a quantum half subtracter and a restorer and a quantum full subtracter and a restorer, and an n-bit quantum mold 2 is formed by the quantum half subtracter, the quantum full subtracter and the restorerⁿA design method of a subtracter; finally, the designed die 2 is utilizedⁿSubtracter for realizing mode 2 based on quantum superposition stateⁿAnd (4) carrying out subtraction operation.

2. According to the rightThe quantum stacking state-based mode 2 of claim 1ⁿThe design method of the subtracter is characterized in that the design method of the quantum half subtracter and the resetter is as follows:

the design circuit of the quantum half-subtracter is realized by four controlled gates and is represented by a symbol Q; the four controlled gates comprise a controlled NOT gate, two controlled V gates and a controlled V⁺A door; the connection sequence of these four controlled gates is: controlled V⁺A gate, a controlled V gate, a controlled NOT gate, a controlled V gate;

applying a quantum half-reducer to a quantum state | c_i>|b_i>|a_i>Obtaining:

whereinIs an exclusive OR operation, c_i,b_i,a_i∈{0,1}，When | c_i>＝|0>Then, the above formula shows that the quantum half-subtracter realizes the subtraction (b)_i-a_i) Wherein the first qubit of the outputMemory subtraction (b)_i-a_i) Borrow information of (1), second qubit of outputStored is the subtracted difference;

in order to reset the auxiliary qubit after the subtraction operation to the initial state, a resetter of the quantum half-subtractor is designed, consisting of five controlled gates, denoted by the symbol Q_oShowing that five controlled gates include two controlled NOT gates, two controlled V gates and one controlled V⁺A door; the connection sequence of these five controlled gates is: to be receivedControl V⁺A gate, a controlled V gate, a controlled NOT gate;

application of a quantum half-reset to a quantum stateObtaining:

whereinIs an exclusive OR operation, c_i,b_i,a_i∈{0,1}，Represented by the formula Q (| c)_i>|b_i>|a_i>) The resetter of the quantum half-subtractor will be knownReset to | c_i>；

The complexity of the quantum decrementer is 4 and the corresponding resetter is 5.

3. A quantum superposition state based mode 2 according to claim 1ⁿThe design method of the subtracter is characterized in that the design method of the quantum full subtracter and the resetter is as follows:

designing a quantum full-reduction device design circuit by utilizing six controlled gates, wherein the quantum full-reduction device is represented by a symbol S; the six controlled gates comprise two controlled NOT gates, three controlled V gates and one controlled V⁺A door; the connection sequence of the six controlled gates is: controlled V gate, controlled not gate, controlled V⁺A gate, a controlled V-gate;

applying a quantum full subtracter to a quantum state | c_i>|b_i>|a_i>|c_i-1>Obtaining:

whereinIs an exclusive OR operation, c_i,b_i,a_i,c_i-1∈{0,1}，When | c_i>＝|0>Then, the above formula shows that the quantum full subtracter realizes the subtraction (b)_i-a_i-c_i-1) Wherein the first qubit of the outputMemory subtraction (b)_i-a_i-c_i-1) Borrow information of (1), second qubit of outputStored is the subtracted difference;

in order to reset the subtracted auxiliary qubit to the initial state, the resetter of the full quantum subtracter, consisting of eight controlled gates, is designated by the symbol S₁Represents; the eight controlled gates include four controlled NOT gates, three controlled V gates and one controlled V⁺A door; the 8 controlled gates are connected in sequence of controlled V gate, controlled NOT gate, controlled V gate, controlled NOT gate and controlled V gate⁺A gate, a controlled V gate, a controlled NOT gate;

application of a restorer of a quantum subtractor to quantum statesObtaining:

whereinIs an exclusive OR operation, c_i,b_i,a_i,c_i-1∈{0,1}，The restorer of the quantum full-subtracting device can be known from the formula (6)Reset to | c_i>；

The complexity of the quantum full subtracter is 6, and the corresponding restorer is 8.

4. A quantum superposition state based mode 2 according to claim 1ⁿThe design method of the subtracter is characterized in that the quantum mode 2 of the n quantum bitⁿThe design method of the subtracter is as follows:

design of modulo-2 of n qubits using quantum half-reducers, quantum full-reducers and corresponding resetsⁿLines of subtractors, modulo-2 of n qubitsⁿSymbol M for subtracter_URepresents;

modulo 2 of n qubitsⁿThe subtracter consists of (n-1) quantum full subtracters, (n-2) restorer of quantum full subtracter, 1 quantum half subtracter and 1 restorer of quantum half subtracter, and it realizes the modulo-2 of two n-bit integersⁿSubtraction operation;

suppose the n-bit integers a and b are stored in the ground states of two n qubits as follows:

wherein, a_n-1a_n-2...a₀And b_n-1b_n-2...b₀Binary representations of integers a and b, respectively, a_h,b_h∈{0,1},h＝0,...,n-1；

Quantum ground state with n qubits addedThe most subtractive auxiliary bits, and arranged in order to obtain |0b_n-1a_{n- 1}0b_n-2a_n-2...0b₀a₀>As an input; mold 2 is put intoⁿThe subtracter is applied to |0b_n-1a_n-10b_n-2a_n-2...0b₀a₀>Obtaining:

M_U|0b_n-1a_n-10b_n-2a_n-2...0b₀a₀>＝|d_nd_n-1a_n-10d_n-2a_n-2...0d₀a₀>；

wherein d is_nRepresenting the sign bit, d_n0 represents a positive number, d_n1 denotes a negative number, d_n-1d_n-2...d₀Is an integer [ (b-a) mod2ⁿ]Binary representation of d_h∈{0,1},h＝0,...,n-1；

From the above formula, die 2ⁿThe subtracter realizes the following modulo-2ⁿSubtraction:

implementing a quantum mode 2 of an n-bit integerⁿThe complexity of the subtraction is 6(n-1) +8(n-2) +4+5 ═ 14n-13, n ≧ 2.

5. A quantum superposition state based mode 2 according to claim 1ⁿThe design method of the subtracter is characterized in that the modulus 2 based on the quantum superposition stateⁿThe subtracter operation implementation method comprises the following steps:

2^mcolumn vector of individual elementsStored in a quantum superposition state of (n + m) qubits

Wherein b (j) is an n-bit integer, j 0^m-1, n and m are all positive integers;

mold 2 is put intoⁿSubtractor M_UAndtensor operation to obtain new quantum operationWherein the symbolsIs a tensor operation symbol; will be provided withThe following applies to the following formula,

obtaining:

wherein a is_n-1a_n-2...a₀、b(j)_n-1b(j)_n-2…b(j)₀And d (j)_n-1d(j)_n-2…d(j)₀Binary representations of integers a, b (j), and d (j), respectively; d (j) ═ b (j) -a) mod2ⁿ；a_h,b(j)_h,d(j)_hE {0,1 }; h is 0,1, …, n-1, n, m is an integer; d (j)_nRepresenting the sign bit of d (j) -a; d (j)_n0 represents a positive number; d (j)_n1 represents a negative number;

according to the formula, the compound has the advantages of,realize the following die 2ⁿSubtraction:

wherein,namely, the following subtraction is implemented:

6. a mode 2 based on quantum superposition state according to claim 5ⁿMethod for designing a subtractor, characterized in that said modulo-2 isⁿSubtraction from a quantum mode 2 of n qubitsⁿA subtractor and a line of m qubits.

7. A mode 2 based on quantum superposition state according to claim 5ⁿMethod for designing a subtractor, characterized in that said modulo-2 isⁿSubtraction operation of n-1 qubit ground states for auxiliary operationsAnd a die 2ⁿQuantum state | ψ of subtractive memory operations_(a-b)>|a>Do not become entangled and are therefore not entangled in the mould 2ⁿAnd the subtraction operation is removed after finishing.

8. A mode 2 based on quantum superposition state according to claim 5ⁿMethod for designing a subtractor, characterized in that said modulo-2 isⁿThe complexity of a subtraction circuit is 14n-13, and 2 can be realized in parallel^mN bits integer modulo 2ⁿAnd (4) carrying out subtraction operation.