CN108647161A - A kind of hardware observation circuit of record memory access address history - Google Patents

Abstract

A hardware monitoring circuit for recording memory access address history, including a monitoring area configuration unit, an arbitration control unit, a flag memory, a flag bit counting unit, a priority content addressable memory bank j, a secondary priority content addressable memory bank, and multiple path selector. Compared with the prior art, the present invention can monitor a plurality of non-continuous address spaces by adopting two-level priority content addressing storage bodies, and the monitoring granularity can be configured and selected to realize the compromise optimization between the monitoring range and the monitoring granularity. Provides hardware support for the synchronization process of data information after a single computer loses synchronization in a hot backup computer.

Description

A hardware monitoring circuit for recording memory access address history

technical field

The invention relates to a hardware monitoring circuit for recording memory access address history.

Background technique

During the continuous and stable operation of the hot backup computer, due to various failures, one stand-alone computer will lose synchronization with other stand-alone computers, which will cause the whole hot backup computer to degrade. In order to improve the reliability and life of the hot backup computer, it is of great significance to reintroduce the out-of-synchronization stand-alone machine caused by the transient failure into the operation of the hot backup computer. The question of how to reintroduce it into the whole machine of the hot standby computer is the parallel machine problem.

The space station GNCC adopts a five-machine hot-standby fault-tolerant configuration, of which four stand-alone machines have processing capabilities, and one stand-alone machine has no processing capabilities. According to the GNCC operation process, the difference between the out-of-synchronization stand-alone and the normal stand-alone lies in the difference in field information. On-site information can be divided into two categories: 1) time information; 2) data information. Therefore, the out-of-synchronization stand-alone computer must complete time synchronization and data synchronization to restore synchronization with other normal stand-alone computers. The present invention mainly provides hardware support for the synchronization of on-site data information of the out-of-synchronization computer through a hierarchical monitoring method for memory access addresses.

Contents of the invention

The technical problem solved by the present invention is to overcome the deficiencies of the prior art, provide a hardware monitoring circuit for recording the memory access address history, overcome the deficiency that the traditional processor access address history cannot be recorded, and adopt two levels of priority content Addressing memory banks can monitor multiple non-contiguous address spaces. The monitoring granularity can be configured and selected to achieve a compromise between monitoring range and monitoring granularity. It provides a data synchronization process for a single machine out of sync in a hot backup computer. Hardware support.

The technical solution of the present invention is: a hardware monitoring circuit for recording memory access address history, including a monitoring area configuration unit, an arbitration control unit, a flag memory, a flag bit counting unit, a priority content addressable memory bank j, a secondary priority level content addressable memory banks, multiplexers;

The monitoring area configuration unit configures the monitoring address range, monitoring address granularity, and monitoring enablement according to external task requirements, and sends the configured monitoring address range, monitoring address granularity, and monitoring enablement to the arbitration control unit, and monitors according to the configuration. The address range configures the monitoring start address register and the monitoring end address register, and the configuration value of the monitoring start address register is less than the monitoring end address register; the monitoring address granularity is 16n bytes and not greater than 1024 bytes, where n is integer;

The arbitration control unit monitors the write enable signal of the bus to be monitored, and when the address to be monitored is in the monitored address range and the write enable signal of the bus to be monitored is valid, judges the granularity of the monitored address, and generates a flag if the granularity of the monitored address is 16n bytes The memory write signal is valid and the write address is the n+8th bit to the n-1th bit of the address to be monitored, a total of 10 bits, and the mark memory write signal and write address are sent to the mark bit counting unit and the mark memory;

Tag memory, receive the tag memory write signal and write address for tag storage, when the tag memory write signal is valid, set the bit position corresponding to the write address to 1, and the remaining bits remain unchanged; the value corresponding to the 1024 bits in the tag memory Send to the mark position counting unit; The numerical value corresponding to 1024 bits in the mark memory is packed 32 consecutively, obtain 32 numerical value packets and send to 32 priority content addressable storage bodies respectively;

The flag bit counting unit receives the value corresponding to 1024 bits in the flag memory, the flag memory write signal, and the write address. When the write enable signal is valid and the bit in the flag memory corresponding to the write address is 0, the flag bit counting unit plus 1;

Priority content addressable memory bank j, wherein j is a positive integer not greater than 32, receives a 32-bit value packet, generates monitoring valid flag j, and priority address output j; wherein, if the priority content addressable memory bank j receives The 32-bit value package is all 0, and the monitoring effective flag j is 0, otherwise the monitoring effective flag j is 1; when the kth bit in the 32-bit value is 1 and the 0th to k-1 bits are 0, the priority address Output j is the 5-bit binary of k, wherein, k=1, 2, 3, ..., 31, when the 0th bit in the 32-bit value is 1, the priority address output j is 00000; the priority address output j is sent to The way selector sends the monitoring effective flag j to the secondary priority content addressable storage body;

The second-level priority content addressing storage body receives the monitoring effective flag j, obtains the 32-bit monitoring effective flag data packet, and generates the monitoring effective flag and the high bit of the effective address; wherein, if the 32-bit monitoring effective flag data packet is all 0, The monitoring effective flag is 0, otherwise the monitoring effective flag is 1; when the kth bit of the 32-bit monitoring effective flag data packet is 1 and the 0th to k-1 bits are 0, the high bit of the effective address is the 5-bit binary of k, Wherein, k=1, 2, 3, ..., 31, when the 0th bit of the 32-bit monitoring effective flag data packet is 1, the high bit of the effective address is 00000; the high bit of the effective address is sent to the multiplexer;

The multiplexer receives the high bit of the effective address and the output j of the priority address, and uses the output j of the priority address corresponding to the high bit of the effective address as the low bit of the effective address.

The monitoring granularity can be configured, and multiple discontinuous address spaces can be monitored.

The advantage of the present invention compared with prior art is:

(1) The present invention solves the problem of excessive time overhead of the current manual circuit design by automatically generating the C unit circuit structure based on the combinational logic output interface, and has the advantage of being able to realize the reinforcement of the C unit of the combinational logic unit in batches;

(2) The present invention uses two-level priority content addressing storage body, compared with sequential query mode, has higher query efficiency, compared with the first-level query method of direct parallel query, has higher evaluation frequency;

(3) The structure of the present invention can monitor a plurality of discontinuous address spaces, and the monitoring granularity can be configured and selected to realize the compromise optimization between the monitoring range and the monitoring granularity, which has good use value.

Description of drawings

Fig. 1 is the overall circuit structure diagram of the present invention;

FIG. 2 is a schematic diagram of the structure of a content addressable memory bank.

Detailed ways

A hardware monitoring circuit for recording the memory access address history, which overcomes the above-mentioned shortcomings that the traditional processor memory access address history cannot be recorded, and can monitor multiple discontinuous address spaces by using two-level priority content addressing memory banks , the monitoring granularity can be configured and selected to realize the compromise optimization between the monitoring range and the monitoring granularity, and provide hardware support for the data information synchronization process after the stand-alone out-of-sync in the hot backup computer.

The monitoring area configuration unit configures the monitoring address range, monitoring address granularity, and monitoring enablement according to external task requirements, and sends the configured monitoring address range, monitoring address granularity, and monitoring enablement to the arbitration control unit, and monitors according to the configuration. The address range configures the monitoring start address register and the monitoring end address register, and the configuration value of the monitoring start address register is less than the monitoring end address register; the monitoring address granularity is 16n bytes and not greater than 1024 bytes, where n is Integer; monitoring granularity can be configured, and multiple non-contiguous address spaces can be monitored.

The arbitration control unit monitors that the write enable signal of the bus to be monitored is valid, and when the address to be monitored is in the monitored address range and the write enable signal of the bus to be monitored is valid, judges the granularity of the monitored address, and if the granularity of the monitored address is 16n bytes, generates The flag memory write signal is valid and the write address is the n+8th bit to the n-1th bit of the address to be monitored, a total of 10 bits, and the flag memory write signal and write address are sent to the flag bit counting unit and the flag memory.

Tag memory, receive the tag memory write signal and write address for tag storage, when the tag memory write signal is valid, set the bit position corresponding to the write address to 1, and the remaining bits remain unchanged; the value corresponding to the 1024 bits in the tag memory Sent to the tag bit counting unit; 32 consecutive values corresponding to 1024 bits in the tag memory are packed to obtain 32 value packets and sent to 32 priority content addressable memory banks respectively.

The flag bit counting unit receives the value corresponding to 1024 bits in the flag memory, the flag memory write signal, and the write address. When the write enable signal is valid and the bit in the flag memory corresponding to the write address is 0, the flag bit counting unit plus 1.

Priority content addressable memory bank j, wherein j is a positive integer not greater than 32, receives a 32-bit value packet, generates monitoring valid flag j, and priority address output j; wherein, if the priority content addressable memory bank j receives The 32-bit value package is all 0, and the monitoring effective flag j is 0, otherwise the monitoring effective flag j is 1; when the kth bit in the 32-bit value is 1 and the 0th to k-1 bits are 0, the priority address Output j is the 5-bit binary of k, wherein, k=1, 2, 3, ..., 31, when the 0th bit in the 32-bit value is 1, the priority address output j is 00000; the priority address output j is sent to The way selector sends the monitoring effective flag j to the secondary priority content addressable memory bank.

The second-level priority content addressing storage body receives the monitoring effective flag j, obtains the 32-bit monitoring effective flag data packet, and generates the monitoring effective flag and the high bit of the effective address; wherein, if the 32-bit monitoring effective flag data packet is all 0, The monitoring effective flag is 0, otherwise the monitoring effective flag is 1; when the kth bit of the 32-bit monitoring effective flag data packet is 1 and the 0th to k-1 bits are 0, the high bit of the effective address is the 5-bit binary of k, Among them, k=1, 2, 3, ..., 31, when the 0th bit of the 32-bit monitoring effective flag data packet is 1, the high bit of the effective address is 00000; the high bit of the effective address is sent to the multiplexer.

The multiplexer receives the high bit of the effective address and the output j of the priority address, and uses the output j of the priority address corresponding to the high bit of the effective address as the low bit of the effective address. For example, the high bit of the effective address is 00000, then select the priority address output 0 as the low bit of the effective address, and the high bit of the effective address is 00110, then select the priority address output 6 as the low bit of the effective address. The present invention will be explained and described in detail below in conjunction with the accompanying drawings.

The overall circuit structure of the memory access address classification monitoring method proposed by the present invention is shown in Figure 1. The circuit structure includes a monitoring area configuration unit, an arbitration control unit, a flag bit counting unit, a flag memory, and a two-level priority content addressable memory bank. and a multiplexer.

The monitoring process is as follows: After reset, the value of the tag memory is all '0', when the write enable to be monitored is enabled and the write address to be monitored is within the valid range of the monitoring configuration area, the tag memory corresponding to the write address to be monitored The mapping bit is written as '1', and the flag bit counting unit adds 1. The relationship between the write address to be monitored and the flag memory mapping bit can be configured by the monitoring granularity register. When the same address to be monitored is repeatedly written, the counting value of the flag bit counting unit remains unchanged , after the monitoring information is read out, the corresponding RAM mapping bit is written as '0'. The detailed design of each unit of the circuit structure is as follows:

(1) Monitoring area configuration unit:

This module can configure the range, granularity and monitoring enable of the monitoring address. Each monitoring area configuration unit includes a monitoring start address register and a monitoring end address register. When the configuration value of the monitoring start address register is less than the monitoring end address register, the configuration is valid, and the structure can monitor address writes within the configured address range. access situation. As shown in Figure 1, there are four monitoring area configuration units, and each monitoring area configuration unit has an independent enable configuration bit, so this structure can monitor four discontinuous address spaces. The monitoring area configuration unit can configure the monitoring granularity register, and the register can make a reasonable compromise between the scope to be monitored and the granularity to be monitored. The relationship between the range to be monitored, the granularity to be monitored, and the capacity of the tag memory satisfies the following formula:

Monitoring range/monitoring granularity = monitoring tag memory capacity

Table 1 shows the relationship between the configuration value of the monitoring granularity register and the monitoring granularity:

(2) Arbitration control unit:

This module is used to arbitrate and select multiple monitoring area configuration units, and generate tag memory write signals and write addresses by monitoring the bus write enable signal and write address, so as to realize the read and write control of the tag memory.

(3) Mark bit counting unit:

The tag bit refers to a specific bit of the tag memory corresponding to the address to be monitored through the monitoring granularity register. The mark bit counting unit is used to realize the statistics of the change amount of the address to be monitored. When the write enable to be monitored is enabled, and the write address to be monitored is within the effective range of the monitoring configuration area, and the flag bit has not been written, that is, the corresponding flag memory data is '0', the flag bit counting unit is added to 1.

(4) Tag memory:

This module is used to store the information of the address to be monitored that has been changed. When the content of the address to be monitored has been changed, the corresponding bit in the flag memory is 1, otherwise it is 0.

(5) Priority content-addressable memory banks:

The content-addressable memory bank is different from the traditional RAM memory structure, as shown in Figure 2. In the scheme of the present invention, the matching data of the content-addressable storage body is simple, only one bit, which ensures that the structure of the priority content-addressable storage body will not be too complicated, and at the same time, there must be multiple addresses and When the data to be matched is matched, the effective address output is the matching address with the highest priority. If there is no data at an address in the entire priority content addressable memory bank that can match the data '1', the match flag outputs '0', Otherwise output '1'.

The present invention adopts two levels of priority content addressing storage body, the input of the first level is the data of the tag memory, which is equivalent to performing block statistics on the data of the tag memory, and the output is the low effective address and the matching flag; the content of the second level of priority The addressable memory bank input is the matching flag of multiple first-level priority content-addressable memory banks, and the output is the high-order effective address and the matching flag of the entire system.

Compared with the sequential query mode under the control of the state machine, the two-level priority content addressing storage body query method of the present invention benefits from the parallelism of the query, greatly improving the efficiency of the query, and compared with the first-level query method of direct parallel query In contrast, the method in this paper divides the query pipeline reasonably and improves the working frequency of the whole system.

(6) Multiplexer:

The multiplexer module is used to strobe and output the effective addresses of multiple first-level priority content-addressable memory banks, and the gating basis comes from the high-order address output of the second-level priority content-addressable memory banks .

The content that is not described in detail in the description of the present invention belongs to the well-known technology of those skilled in the art.

Claims (2)

1. A hardware monitoring circuit for recording memory access address history, characterized in that it includes a monitoring area configuration unit, an arbitration control unit, a tag memory, a tag bit counting unit, a priority content addressing storage body j, and a secondary priority content addressing unit. Address memory bank, multiplexer; The monitoring area configuration unit configures the monitoring address range, monitoring address granularity, and monitoring enablement according to external task requirements, and sends the configured monitoring address range, monitoring address granularity, and monitoring enablement to the arbitration control unit, and monitors according to the configuration. The address range configures the monitoring start address register and the monitoring end address register, and the configuration value of the monitoring start address register is less than the monitoring end address register; the monitoring address granularity is 16n bytes and not greater than 1024 bytes, where n is integer; The arbitration control unit monitors the write enable signal of the bus to be monitored, and when the address to be monitored is in the monitored address range and the write enable signal of the bus to be monitored is valid, judges the granularity of the monitored address, and generates a flag if the granularity of the monitored address is 16n bytes The memory write signal is valid and the write address is the n+8th bit to the n-1th bit of the address to be monitored, a total of 10 bits, and the mark memory write signal and write address are sent to the mark bit counting unit and the mark memory; Tag memory, receive the tag memory write signal and write address for tag storage, when the tag memory write signal is valid, set the bit position corresponding to the write address to 1, and the remaining bits remain unchanged; the value corresponding to the 1024 bits in the tag memory Send to the mark position counting unit; The numerical value corresponding to 1024 bits in the mark memory is packed 32 consecutively, obtain 32 numerical value packets and send to 32 priority content addressable storage bodies respectively; The flag bit counting unit receives the value corresponding to 1024 bits in the flag memory, the flag memory write signal, and the write address. When the write enable signal is valid and the bit in the flag memory corresponding to the write address is 0, the flag bit counting unit plus 1; Priority content addressable memory bank j, wherein j is a positive integer not greater than 32, receives a 32-bit value packet, generates monitoring valid flag j, and priority address output j; wherein, if the priority content addressable memory bank j receives The 32-bit value package is all 0, and the monitoring effective flag j is 0, otherwise the monitoring effective flag j is 1; when the kth bit in the 32-bit value is 1 and the 0th to k-1 bits are 0, the priority address Output j is the 5-bit binary of k, wherein, k=1, 2, 3, ..., 31, when the 0th bit in the 32-bit value is 1, the priority address output j is 00000; the priority address output j is sent to The way selector sends the monitoring effective flag j to the secondary priority content addressable storage body; The second-level priority content addressing storage body receives the monitoring effective flag j, obtains the 32-bit monitoring effective flag data packet, and generates the monitoring effective flag and the high bit of the effective address; wherein, if the 32-bit monitoring effective flag data packet is all 0, The monitoring effective flag is 0, otherwise the monitoring effective flag is 1; when the kth bit of the 32-bit monitoring effective flag data packet is 1 and the 0th to k-1 bits are 0, the high bit of the effective address is the 5-bit binary of k, Wherein, k=1, 2, 3, ..., 31, when the 0th bit of the 32-bit monitoring effective flag data packet is 1, the high bit of the effective address is 00000; the high bit of the effective address is sent to the multiplexer; The multiplexer receives the high bit of the effective address and the output j of the priority address, and uses the output j of the priority address corresponding to the high bit of the effective address as the low bit of the effective address. 2. The hardware monitoring circuit for recording memory access address history according to claim 1, characterized in that: the monitoring granularity can be configured, and multiple discontinuous address spaces can be monitored.