CN108055202A

CN108055202A - A kind of message processor and method

Info

Publication number: CN108055202A
Application number: CN201711288346.6A
Authority: CN
Inventors: 任岚晖
Original assignee: Ruijie Networks Co Ltd
Current assignee: Ruijie Networks Co Ltd
Priority date: 2017-12-07
Filing date: 2017-12-07
Publication date: 2018-05-18
Anticipated expiration: 2037-12-07
Also published as: CN108055202B

Abstract

The invention discloses a kind of message processor and method, for the processing by carrying out message based on CPU+FPGA heterogeneous systems.The equipment includes central processor CPU and at least one on-site programmable gate array FPGA；The list item configuration information for configuring the list item for configuring list item for FPGA, and is sent to the FPGA by the CPU；The storage address of the list item is carried in the list item configuration information；At least one FPGA, for receiving the list item configuration information and clear text, intercept the header field of the clear text, and the keyword tabled look-up is extracted from header field, it is tabled look-up according to the list item that the keyword and the storage address store, the clear text is handled according to checking result, it will treated message is sent to equipment corresponding with treated the message；Wherein, the keyword is corresponding with the list item that the storage address stores.

Description

Message processing equipment and method

Technical Field

The present invention relates to the field of network technologies, and in particular, to a message processing apparatus and method.

Background

At present, the architecture of the Network device is mainly an integrated circuit (ASIC) architecture, or an NP (Network Processor) architecture, or a CPU (Central Processing Unit) architecture.

The ASIC architecture has relatively fixed functions only for specific service scenarios, so that the performance is relatively high, but due to the relatively fixed functions, the ASIC architecture has low programmability, and cannot meet the requirements of variable services. The NP framework is composed of a plurality of microcode processors and a plurality of hardware coprocessors, the plurality of microcode processors run in parallel inside, and the processing flow is controlled by a preprogrammed microcode (microcode), so that the NP framework has strong programmability, but is expensive. In addition, the multi-core CPU architecture can realize service functions on the multi-core CPU by adopting software programming, and has strong programmability, but the performance of the multi-core CPU architecture is inferior to that of other architectures. Therefore, the architecture of the current network device has more or less these defects, so that the Field-Programmable gate Array (FPGA) architecture is gradually adopted. The FPGA has extremely high programmability and has strong advantages in the aspects of time delay, throughput rate and the like. However, at present, for a network device of an FPGA architecture, there is no universal development model or a relatively fixed network message processing method, so development is redesigned almost every time, and module interfaces are different, reusability is low, a design can be completed only when a developer is familiar with a processing framework and a message processing logic, and for a developer who only needs to verify a certain algorithm, a protocol, or even a certain unit processing logic, it takes a lot of time to build a complete network message processing framework, and development efficiency is low.

Disclosure of Invention

The embodiment of the invention provides message processing equipment and a message processing method, which are used for processing messages through a heterogeneous system based on a CPU + FPGA.

In a first aspect, a message processing device is provided, which comprises a central processing unit CPU and at least one field programmable gate array FPGA;

the CPU is used for configuring table items for the FPGA and sending table item configuration information for configuring the table items to the FPGA; the table item configuration information carries the storage address of the table item;

the at least one FPGA is used for receiving the table item configuration information and the message to be processed, intercepting the message header field of the message to be processed, extracting keywords for table lookup from the message header field, performing table lookup according to the keywords and the table items stored in the storage address, processing the message to be processed according to the table lookup result, and sending the processed message to equipment corresponding to the processed message; wherein the keyword corresponds to an entry stored by the storage address.

Optionally, any one of the at least one FPGA includes a plurality of functional units, where the plurality of functional units specifically include:

a message receiving RX unit, configured to receive a message to be processed;

the message packet splitting Decap unit is used for intercepting the message header field of the message to be processed and sending other fields except the message header field in the message to be processed to a message buffer PacketBuffer unit included by the FPGA for storage;

a packet parsing Parser unit, configured to determine the type of the packet to be processed according to the packet header field, and add an upload CPU flag in the packet header field when the determination result indicates that the packet to be processed is a protocol packet; wherein, the CPU mark indicates that the message to be processed needs to be sent to the CPU;

the keyword extraction Fetch unit is used for extracting keywords in the header field of the message;

a table look-up engine unit, configured to perform table look-up according to the keyword and the table entry stored in the storage address, and modify the header field of the message according to the table look-up result;

a message encapsulation Encap unit, configured to determine whether to encapsulate the to-be-processed message according to the modified message header field; if the message to be processed needs to be encapsulated, encapsulating the modified message header field and other fields except the message header field in the message to be processed stored in the PacketBuffer unit;

a message sending TX unit, configured to determine whether the encapsulated message includes the uplink CPU flag; and if so, uploading the packaged message to the CPU.

Optionally, the table lookup engine unit includes at least one table lookup engine, and each table lookup engine includes:

the Match subunit is used for formatting the keywords extracted by the keyword extraction Fetch unit according to a format which can be identified by the Table entry Table subunit included in the Table look-up engine;

the Table entry Table subunit is used for performing Table lookup according to the formatted keywords and the Table entries stored in the storage address and outputting the Table lookup result; wherein, the Table item Table subunit stores a Table look-up algorithm for Table look-up;

and the modification Action subunit is used for modifying the header field of the message according to the table look-up result.

Optionally, each table lookup engine further includes:

and the Table entry management tableng subunit is used for configuring the Table entries which can be inquired by the Table entry Table subunit in the same inquiry engine according to the Table entry configuration information.

Optionally, the CPU includes a Main management Host Main unit and a first control unit, the plurality of functional units further include a second control unit,

the Main management Host Main unit is used for generating a control signal; the control signal carries the ID of one functional unit included in the plurality of functional units; wherein the IDs of different functional units in any one of the at least one FPGA are different;

the first control unit is used for sending the control signal to the second control unit;

the second control unit is used for receiving the control signal and forwarding the control signal to the functional unit corresponding to the ID; and the at least one FPGA can control the starting of the function realized by the functional unit corresponding to the ID and/or the parameter setting based on the control signal.

Optionally, the CPU further includes a message transceiving unit; the plurality of functional units further comprise a direct memory access unit, and the direct memory access unit is connected with the message receiving RX unit and the message sending TX unit;

the message receiving and sending unit is used for storing the message to be processed in the memory and sending the storage address of the message to be processed to the direct memory access unit; or receiving the storage address of the message carrying the CPU mark sent by the direct memory access unit, and acquiring the message carrying the CPU mark according to the storage address of the message carrying the CPU mark;

the direct memory access unit is configured to receive a storage address of the to-be-processed packet, read the to-be-processed packet according to the storage address of the to-be-processed packet, and send the read to-be-processed packet to the packet receiving RX unit; or, receiving the message carrying the CPU mark sent by the message sending TX unit, storing the message carrying the CPU mark in a memory, and sending the storage address of the message carrying the CPU mark to the message receiving and sending unit.

Optionally, the CPU further includes a first table item configuration unit; the plurality of function units further comprise a second table item configuration unit, and the second table item configuration unit is connected with the table item management tablemsng subunit in each table look-up engine;

the Main management Host Main unit is also used for generating table item configuration information;

the first table item configuration unit is configured to send the table item configuration information to the second table item configuration unit;

and the second table item configuration unit is configured to receive the table item configuration information, and forward the table item configuration information to a main management tablemsng subunit corresponding to the type according to the type of the table item configured by the table item configuration information.

Optionally, the CPU further includes a message source MAC address learning unit;

and the message source MAC address learning unit is used for storing keywords included in the message carrying the uploading CPU mark and sending a storage address to the second table item configuration unit.

Optionally, any one of the at least one FPGA further includes:

the message transmission channel is used for transmitting messages;

the message header transmission channel is used for transmitting a message header field;

a message header control field transmission channel for transmitting a message header control field;

the table item configuration information transmission channel is used for transmitting the table item configuration information;

a req/ack signal path for transmitting a req/ack signal;

when any one of the plurality of functional units transmits data to other functional units, the any one functional unit can call a channel corresponding to the type of the data to be transmitted for transmission.

In a second aspect, a method for processing a packet is provided, where the method is applied to a packet processing device, the packet processing device includes a CPU and at least one FPGA, and the method includes:

the at least one FPGA receives table item configuration information of table items configured for the FPGA by the CPU; the table item configuration information carries the storage address of the table item;

the at least one FPGA receives the table item configuration information and the message to be processed, intercepts the message header field of the message to be processed, extracts keywords for table lookup from the message header field, performs table lookup according to the keywords and the table items stored in the storage address, processes the message to be processed according to the table lookup result, and sends the processed message to a device corresponding to the processed message; wherein the keyword corresponds to an entry stored by the storage address.

Optionally, the method further includes:

the at least one FPGA receives a message to be processed;

the at least one FPGA intercepts the message header field of the message to be processed and stores other fields except the message header field in the message to be processed;

the at least one FPGA determines the type of the message to be processed according to the message header field, and adds a CPU uploading mark in the message header field when the determination result shows that the message to be processed is a protocol message; wherein, the CPU mark indicates that the message to be processed needs to be sent to the CPU;

the at least one FPGA extracts keywords in the message header field;

the at least one FPGA carries out table lookup according to the keywords and the table items stored by the storage addresses, and modifies the header fields of the messages according to the table lookup results;

the at least one FPGA determines whether the message to be processed needs to be packaged according to the modified message header field; if the message to be processed needs to be encapsulated, encapsulating the modified message header field and other fields except the message header field in the message to be processed stored in the PacketBuffer unit;

the at least one FPGA determines whether the packaged message comprises the uploading CPU mark; and if the result is positive, the packaged message is sent to the CPU.

Optionally, the table lookup performed by the at least one FPGA according to the keyword and the table entry stored in the storage address, and modifying the header field of the packet according to the table lookup result includes:

the at least one FPGA formats the extracted keywords according to a format which can be identified by the at least one FPGA;

the at least one FPGA carries out table lookup according to the formatted keywords and the table entries stored by the storage addresses, and outputs the table lookup result; wherein the at least one FPGA stores a table lookup algorithm for table lookup;

and the at least one FPGA modifies the message header field according to the table look-up result.

Optionally, the method further includes:

and the at least one FPGA configures the table entry which can be inquired by the at least one FPGA according to the table entry configuration information.

Optionally, the method further includes:

the at least one FPGA receives a control signal sent by the CPU; the FPGA comprises a plurality of functional units, and the IDs of different functional units in any one FPGA are different; the control signal carries the ID of one functional unit included in the plurality of functional units;

the at least one FPGA sends the control signal to a functional unit corresponding to the ID; and the FPGA can control the starting of the function realized by the functional unit corresponding to the ID and/or parameter setting based on the control signal.

Optionally, the method further includes:

the at least one FPGA receives a storage address of a message to be processed sent by the CPU; reading the message to be processed according to the storage address of the message to be processed;

or,

and the at least one FPGA carries the message carrying the CPU mark to be stored in the memory, and sends the storage address of the message carrying the CPU mark to the CPU.

Optionally, the method further includes:

the at least one FPGA receives table item configuration information sent by the CPU;

and the at least one FPGA configures table entries according to the table entry configuration information.

Optionally, any one of the at least one FPGA further includes:

the message transmission channel is used for transmitting messages;

a req/ack signal path for transmitting a req/ack signal;

In a third aspect, a method for processing a packet is provided, where the method is applied to a packet processing device, the packet processing device includes a CPU and an FPGA, and the method includes:

the CPU generates table item configuration information; the table item configuration information is used for configuring table items for the FPGA, and the table item configuration information carries storage addresses of the table items;

and the CPU sends the table item configuration information for configuring the table item to the FPGA.

Optionally, the method further includes:

the CPU generates a control signal; the control signal carries the ID of one of the functional units included in the FPGA;

and the CPU sends the control signal to the FPGA so that the FPGA can control the starting of the function realized by the functional unit corresponding to the ID and/or the parameter setting based on the control signal.

Optionally, the method further includes:

the CPU stores the message to be processed in the memory and sends the storage address of the message to be processed to the FPGA;

or,

and the CPU receives the storage address of the message carrying the CPU mark sent by the FPGA and reads the message carrying the CPU mark according to the storage address.

Optionally, after reading the message carrying the CPU flag according to the storage address, the method further includes:

the CPU stores the keywords included in the message carrying the uploading CPU mark;

and the CPU sends a storage address to the FPGA.

In the embodiment of the invention, the message processing equipment is equipment based on a CPU + FPGA heterogeneous system, wherein the CPU is used for controlling and managing functions of the FPGA, the FPGA is used for specifically processing and forwarding messages, and the processing of the universal network messages is realized through the cooperative work of the CPU and the FPGA, so that the requirements of application scenes such as network message processing algorithm verification, network protocol unloading realization and the like can be met.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a message processing apparatus according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a message processing apparatus including a CPU and an FPGA according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a message processing apparatus for processing a two-layer message according to an embodiment of the present invention;

fig. 4 is a flowchart illustrating a message processing method according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.

The technical background of the embodiments of the present invention is described below.

At present, because of the extremely strong programmability of the FPGA and the strong advantages in the aspects of delay, throughput, and the like, network devices based on the FPGA architecture are gradually being adopted. However, at present, for a network device of an FPGA architecture, there is no universal development model or a relatively fixed network message processing method, so development is redesigned almost every time, and module interfaces are different, reusability is low, a design can be completed only when a developer is familiar with a processing framework and a message processing logic, and for a developer who only needs to verify a certain algorithm, a protocol, or even a certain unit processing logic, it takes a lot of time to build a complete network message processing framework, and development efficiency is low.

In view of this, an embodiment of the present invention provides a message processing apparatus, which is an apparatus based on a CPU + FPGA heterogeneous system, where the CPU is configured to control and manage functions of the FPGA, and the FPGA is configured to specifically process and forward a message, and the CPU and the FPGA cooperate to implement processing of a general network message, so as to meet requirements of application scenarios such as network message processing algorithm verification and network protocol offload.

The technical scheme provided by the embodiment of the invention is described below by combining the accompanying drawings.

Referring to fig. 1, an embodiment of the present invention provides a message processing apparatus 10, which includes a CPU and at least one FPGA, wherein the CPU is connected to the FPGA through a Peripheral Component Interconnect express (PCIe) bus. Since the message processing processes in each FPGA are the same, one of the FPGAs will be described as an example below, and one of the FPGAs may be any one of the at least one FPGA, and hereinafter, one of the FPGAs is directly referred to as an FPGA for short.

In the embodiment of the present invention, the FPGA may be used for carrying a forwarding function of a data plane, that is, for processing and forwarding a packet. Specifically, the FPGA may receive a message to be processed sent by another device or the CPU, extract a message header field of the message to be processed, analyze the message header field, perform table lookup according to the message header field, process the message according to a table lookup result, and then send the processed message to the corresponding device.

In the embodiment of the present invention, the CPU may be configured to carry functions of a control plane and a management plane, that is, configured to configure entries for the FPGA, manage the opening and closing of the functions of the FPGA, set parameters of the FPGA during operation, and the like. The table entry is a table entry when the FPGA performs table lookup according to a keyword included in the message, and may be, for example, a Media Access Control (MAC) Address table entry, an Address Resolution Protocol (ARP) table entry, an Internet Protocol Address (IP) Address table entry, and the like.

Fig. 2 is a schematic structural diagram of an FPGA and a CPU according to an embodiment of the present invention. The FPGA may include a plurality of functional units. The functional units included in the FPGA will be described in detail below, and meanwhile, the functional units included in the CPU will be referred to in the following description.

A Receiver (RX) unit, which may be configured to receive a message to be processed. Specifically, when the message to be processed arrives at the message processing device, the message to be processed is usually received through a physical ethernet port on the message processing device, so that the message receiving RX unit can receive the message to be processed from the physical ethernet port. In addition, the CPU may also serve as an interface for receiving a message to be processed, and therefore, after the CPU receives the message to be processed, the message receiving RX unit may also receive the message to be processed forwarded by the CPU.

A packet splitting (Decap) unit, where the packet splitting Decap unit may be configured to receive, after the message receiving RX unit receives the message to be processed, the message to be processed sent by the message receiving RX unit. Since the header field of a message already contains all the information for message forwarding processing in a message, only the header field of the message needs to be processed. Therefore, after the Decap unit receives the message to be processed, the header field of the message to be processed may be intercepted, and the header field of the message may be used as the object of message processing, and other fields except the header field of the message in the message to be processed do not need to be processed, so that the fields may be stored in the cache. Therefore, the FPGA may further include a packet buffer (PacketBuffer) unit, configured to store other fields except for a header field of the packet in the to-be-processed packet. Generally speaking, the first 128B of a message includes all information used for message forwarding processing, so that the message packet splitting Decap unit may use the first 128B of the message to be processed as a message header field, and store other fields after 128B of the message to be processed into the message buffer packet buffer unit.

A packet parsing (Parser) unit, which may be configured to determine a type of a packet to be processed according to a packet header field. Specifically, when the message to be processed is a protocol message, adding a sending CPU flag in a header field of the message, sending the modified header field of the message to a keyword extraction (Fetch) unit for processing, and sending the sending CPU flag to indicate that the message to be processed needs to be sent to a CPU; and when the message to be processed is not the protocol message, directly sending the header field of the message to a keyword extraction Fetch unit for processing. In addition, the packet parsing Parser unit can also record the number of different packet types.

The keyword extraction Fetch unit may be configured to receive the modified message header field or the message header field sent by the message parsing Parser unit, extract keywords included in the modified message header field, and send the extracted keywords to the table lookup engine unit. The keywords are used for table lookup, and the keywords may be, for example, an MAC address, a source MAC address, a destination IP address, a source IP address, or an Identifier (ID) of a Virtual Local Area Network (VLAN) carried in the packet.

And the table look-up engine unit is used for extracting the keywords extracted by the Fetch unit according to the keywords and looking up the table for the table configured for the table look-up engine unit, and modifying the header field of the message according to the table look-up result.

Specifically, the table lookup engine unit may further include a plurality of table lookup engines, and each table lookup engine may further include a plurality of sub-units. Wherein, a plurality of table lookup engines can be connected in sequence, and the contents of table lookup by each table lookup engine can be different. For example, the lookup engine unit may include two lookup engines, one for performing a lookup via a two-layer MAC address, and the other for performing a lookup via a three-layer IP address. Although the contents of the lookup table may be different, the structure of each lookup table may be similar, and thus the following description will be made by taking the structure of one lookup table as an example.

Specifically, the lookup engine may include:

and the matching (Match) subunit is used for formatting the keywords extracted by the keyword extraction Fetch unit according to a format which can be identified by the Table entry (Table) subunit included in the Table lookup engine. The keyword extracted by the keyword extraction Fetch unit is only to extract the keyword from the header field of the message, but may not be in a format that can be identified by the Table entry Table subunit, so that matching the Match subunit requires combining the keyword, and then sends the combined keyword to the Table entry Table subunit. For example, when the MAC address Table entry is searched, the format of the keyword that can be identified by the Table entry Table subunit is to combine according to the sequence that the VLAN ID is in front and the destination MAC address is in back, then after the keyword extraction Fetch unit extracts the VLAN ID and the destination MAC address respectively, the matching Match subunit needs to combine according to the format that the VLAN ID is in front and the destination MAC address is in back, and then sends the combined keyword to the Table entry Table subunit.

And the Table entry Table subunit is used for performing Table lookup according to the formatted keywords to obtain a Table lookup result. The Table entry Table subunit may further access the Table entries stored in the memory, and the Table entry Table subunit may perform Table lookup on the formatted keywords and the Table entries through the corresponding Table lookup algorithm. Specifically, the Table lookup algorithm encapsulated in the Table entry Table subunit may include a direct index algorithm, a Hash (Hash) algorithm, a multi-Hash algorithm, a Hi-Cuts algorithm, a Longest Prefix Match (LPM) algorithm, and the like. Of course, other possible algorithms may be included, and the embodiment of the present invention is not limited thereto. The Table entries that can be accessed by the Table subunit are configured by the CPU, which will be described in detail later and will not be described herein again. The memory may be a Static Random Access Memory (SRAM); the memory may also be a Double Data Rate (DDR) memory, and of course, other possible memories may also be used, which is not limited in this embodiment of the present invention.

And the modification (Action) subunit is used for modifying the message header field according to the table look-up result and then sending the modified message header field to a subsequent table look-up engine or a subsequent functional unit. In addition, the message header field can also carry the search result. For example, when table lookup is performed through a destination MAC address and a source MAC address, if the table lookup of the source MAC address is not hit, the Action subunit may add a send-up CPU flag in a header field of a message, so that the message can be sent to a CPU for message learning; if the target MAC address is hit, adding a Forwarding (FW) mark in a message header field, and adding a message forwarding outlet in a table look-up result in a message control field, but if the target MAC address is not hit, directly adding a Drop (Drop) mark in the message header field.

In this embodiment of the present invention, the Table lookup engine may further include a Table entry management (TableMng) subunit, where the Table entry management tableng subunit is configured to configure the Table entry that is in the same Table lookup engine as the Table entry management tableng subunit and can be accessed by the Table entry Table subunit.

After the table lookup engine unit outputs the modified message header field, the modified message header field is input to a message encapsulation (Encap) unit. And the message encapsulation Encap unit is used for determining whether the message to be processed needs to be encapsulated according to the modified message header field. Specifically, if the modified message header field does not carry a Drop flag, the message encapsulation Encap unit takes out the remaining field stored in the message cache packet buffer unit, encapsulates the remaining field and the modified message header field, and sends the encapsulated message to a message sending (Transmitter, TX) unit; and if the modified message header field carries a Drop mark, directly discarding the modified message header field, and deleting the rest fields stored in the packet buffer unit of the message buffer.

And the message sending (TX) unit is used for sending the packaged message to corresponding equipment according to the mark carried in the packaged message after receiving the packaged message. Specifically, if the encapsulated message carries a flag of the CPU, the encapsulated message is sent to the CPU; and if the packaged message carries the FW mark, forwarding the packaged message according to a message outlet carried in the packaged message.

In the embodiment of the present invention, the FPGA includes some special functional units in addition to the functional unit for processing the message, and correspondingly, the CPU also includes a corresponding functional unit for completing the interaction between the PFGA and the CPU to assist in completing the message processing flow.

The CPU may include a message transceiver unit, and correspondingly, the FPGA may further include a Direct Memory Access (DMA) unit, and the direct memory Access unit may be connected to the plurality of functional units, for example, may be connected to the message transmitting TX unit and the message receiving RX unit. Specifically, after the CPU receives a new message to be processed, the message transceiver unit may store the message to be processed in the memory, and then send the storage address of the message to be processed to the direct memory access unit in the FPGA, where the direct memory access unit may receive the storage address, read the message to be processed stored in the memory according to the storage address, and then send the message to be processed to the message receiving RX unit in the FPGA, so as to perform subsequent message processing.

In addition, when the message sending TX unit determines that the packaged message carries the CPU mark, the packaged message is also sent to the direct memory access unit, the direct memory access unit stores the packaged message in the memory and sends the storage address to the message transceiving unit in the CPU, and the message transceiving unit can acquire the message carrying the CPU mark according to the storage address of the message carrying the CPU mark.

After the message transceiver unit in the CPU receives the encapsulated message, it may also determine the reason why the encapsulated message carries the CPU flag, for example, the reason may be that the message is a protocol message or a message that is not hit by table lookup. The protocol message is used for transmitting a protocol, and therefore needs to be sent to a CPU for processing; the messages which are not looked up and missed need to be forwarded to a message source MAC address learning unit in the CPU for message learning. For example, if the source MAC address is not hit during table lookup, the message source MAC address learning unit learns the source MAC address and stores the entry generated by learning in the memory, and meanwhile, the information of the newly generated entry needs to be sent to the FPGA, so that the FPGA can be successfully hit during the next table lookup.

In the embodiment of the present invention, the CPU further includes a Host Main unit (Host Main) configured to generate entry configuration information according to a learning result of the message source MAC address learning unit. For example, after the message source MAC address learning unit learns to generate a new entry, it is necessary to notify the FPGA of the related information of the newly generated entry, and at this time, it is necessary to generate entry configuration information through the host management HostMain unit, where the entry configuration information carries a storage address of the newly generated entry.

In order to send the table entry configuration information to the FPGA, a first table entry configuration (TableConfig) unit may be further included in the CPU, and the first table entry configuration unit may be configured to send the table entry configuration information to the FPGA. The first table item configuration unit not only sends the learned table item configuration information of the newly added table items to the FPGA, but also sends the table item configuration information of the table items related to message forwarding to the FPGA when the message processing equipment is initialized; in addition, the table entry configuration information used for deleting part of table entries can be sent to the FPGA.

Correspondingly, the FPGA may further include a second table entry configuration unit, and the second table entry configuration unit may be connected to the table entry management TableMng subunit in each table lookup engine. The second table entry configuration unit may receive the table entry configuration information sent by the first table entry configuration unit, where the table entry configuration information may carry type information used to indicate a type of a newly generated table entry, and then the second table entry configuration unit may send the table entry configuration information to a corresponding table entry management TableMng subunit according to the type information. In addition, when the table entry is large, the second table entry configuration unit may also be responsible for carrying the table entries, for example, carrying the table entries in bulk from the DMA cache of the CPU.

In the embodiment of the invention, the CPU can also control the function and the parameter of the FPGA. Specifically, the Main management Host Main unit in the CPU may be further configured to generate a Control Signal (Control Signal), where the Control Signal is used to Control dynamic configuration, real-time management, register reading and writing, and the like of the functional unit of the FPGA. Specifically, in order to correctly control the functions that can be realized by the specific functional units in the FPGA to perform control and/or parameter setting after the FPGA receives the control signal, the control signal may carry the ID of the functional units included in the FPGA, so that the FPGA can perform more accurate control after receiving the control signal. Wherein the IDs of different functional units in the FPGA are different.

In order to send the control signal to the FPGA, a first control unit may be further included in the CPU, and the first control unit may be configured to send the control signal to the FPGA.

Of course, the Main management Host Main unit may process the control signal and the table entry configuration information, and may also generate other information, for example, may also generate scheduling information for scheduling a function unit in the FPGA to execute a corresponding function, and the like. Correspondingly, other information can also be forwarded to the FPGA via the first control unit.

In order to receive the control signal sent by the CPU, the FPGA may further include a second control unit, and the second control unit may be configured to receive the control signal and forward the control signal to the functional unit corresponding to the ID according to the ID carried in the control signal, so that the corresponding functional unit can execute an action indicated by the control signal. For example, the control signal may be a signal for setting a receiving rate of the message receiving RX unit, and after receiving the control signal, the message receiving RX unit receives the message to be processed according to the receiving rate indicated by the control signal; or, the control signal may also be used to control the on or off of the message learning function of the Table entry Table subunit, where the CPU may turn on the message learning function of the Table entry Table subunit through the control signal, so that the FPGA may directly learn the message that is not hit by Table lookup without sending the message to the CPU; correspondingly, the CPU may also close the message learning function of the Table entry Table subunit through the control signal.

In the embodiment of the present invention, the interaction between the CPU and the FPGA may be implemented by a main Channel (Host Channel) in an Open Computing Language (OpenCL) system provided by a manufacturer of the FPGA. For example, when a first control unit in the CPU wants to send a control signal to a second control unit in the FPGA, the Host Channel may be called by the first control unit to send the control signal.

In addition, some configurable functional units can be reserved in the CPU to implement some functions that other functional units need not have in the CPU, and these units can be configured in the actual operation process. For example, the control packet processing unit is configured to process the control packet.

In the embodiment of the present invention, the FPGA may include the following data transmission channels:

(1) the message transmission channel is used for transmitting messages;

(2) a message header transmission (pkt) channel for transmitting a message header field;

(3) a packet head control (phc) channel for transmitting a packet head control field; the message header control field carries message forwarding control information, such as a header offset value of an MAC layer, or an offset value of an IP header, or information of a flag used for indicating whether a message is discarded or not, or information of a flag used for indicating whether a message is mirrored or not.

(4) A message transmission (msg) channel for transmitting information such as the table entry configuration information;

(5) a req/ack signal path for transmitting a req/ack signal; the req/ack signal is a handshake signal between two functional units, and is used for communication between the two functional units according to a protocol mode agreed by the two functional units.

The data transmission Channel can be realized by a Channel provided by an OpenCL system. The bit width of the message transmission channel and the pkt channel can be 128B, that is, 128B can be transmitted in each transmission beat during message transmission or message header transmission; phc the lane may have a bit width of 64B or 32B; the bit width of the msg channel can be 32B or 16B; the bit width of the req/ack signal path may take 8B or 4B. Of course, the FPGA may further include other possible data transmission channels, which is not limited in this embodiment of the present invention.

When two functional units in the FPGA need to transmit data, a channel corresponding to the type of the data to be transmitted can be called for transmission. Specifically, the data transmission channel may further have a data caching capability, and when data transmission is performed, if the beats of the functional units at the two ends are different, an isolation effect can be achieved. For example, when the rate received by the message receiving RX unit is higher than the capability of the packet splitting Decap unit to process the message, the message transmitted by the message receiving RX unit to the packet splitting Decap unit cannot be processed in time, and at this time, a data transmission channel between the message receiving RX unit and the packet splitting Decap unit is required to cache the message that is not processed in time by the packet splitting Decap unit.

In fig. 2, data transmission channels that may be called between functional units are shown, for example, a header field, a packet or a header control field, or other information may be transmitted between the message receiving RX unit and the packet splitting Decap unit, so that the message receiving RX unit may call a pkt channel, phc channel, or msg channel to send data to the packet splitting Decap unit. When the second table entry configuration unit forwards the table entry configuration information, when the table entry is smaller, the second table entry configuration unit may perform configuration by calling a req/ack signal channel; when the table entry is large, the msg channel can be directly called for configuration through the second table entry configuration unit. The calling modes of the other functional units are similar, and are not described in detail herein. Of course, the invocation of the channel shown in fig. 2 is only for illustration, and therefore there may be other possible invocation situations, which are not limited in this embodiment of the present invention.

Fig. 3 is a schematic structural diagram of a message processing device for processing a layer two message of an ethernet according to an embodiment of the present invention. The following describes the message processing flow of the message processing device shown in fig. 3.

In the embodiment of the present invention, the CPU may send a Packet receiving Rate (Packet Rate Limit) signal to the second control unit in the FPGA through the first control unit, and the signal carries an ID of the Packet receiving RX unit in the FPGA, and after the second control unit receives the Packet Rate Limit signal, the signal is forwarded to the Packet receiving RX unit, and the Packet receiving RX unit may receive a Packet according to the Packet receiving Rate indicated by the Packet Rate Limit signal.

After receiving the message to be processed, the RX unit sends the message to a packet splitting Decap unit. The packet splitting Decap unit intercepts the first 128B field in the message to be processed as the packet header field of the message to be processed, then sends the packet header field to the packet parsing Parser unit, and stores the remaining fields except the 128B field in the packet buffering PacketBuffer unit.

The message parsing Parser unit judges the type of the message according to the message header field, if the judgment result shows that the message to be processed is a protocol message, a sending CPU (central processing unit) identifier is added to the message header field, and the modified message header field is sent to the MAC address extraction Fetch unit; and if the judgment result shows that the message to be processed is not the protocol message, directly sending the message header field to the MAC Fetch unit. The MAC address extraction Fetch unit is a specific unit in the two-layer message processing. The packet parsing Parser unit can also count the number of packets processed by itself and the number of packets of different types, and send the packets to the CPU through the second control unit.

The MAC address extraction Fetch unit extracts a destination MAC address and a source MAC address in a header field of the message, and sends the destination MAC address and the source MAC address into an address Forwarding table (FDB) table look-up engine.

And the matching Match subunit in the FDB Table look-up engine sends a destination MAC address query request and a source MAC address query request to the Hash Table entry Hash Table subunit. The Hash Table entry Hash Table subunit indicates that Table lookup is performed through a Hash algorithm. The Hash Table entry Hash Table subunit calculates a Hash value according to the destination MAC address and the source MAC address, then performs Table lookup according to the Hash value, and sends a Table lookup result to the modification Action subunit. When the source MAC address is not hit, if the CPU configures a source MAC address automatic learning (Auto Learn) function for the Hash Table entry subunit through the first control unit, the Hash Table entry subunit automatically stores the source MAC address, and if the Auto Learn function is closed, the Action subunit is modified to add an uploading CPU mark in a message header field. When the table look-up result shows that the target MAC address is not hit, the Action subunit adds a Drop mark to the header field of the message, and when the table look-up result shows that the target MAC address is hit, the Action subunit is modified, the message outlet is stored into the message control field, and an FW mark is added to the header field of the message.

After the message encapsulation Encap unit receives the modified message header field sent by the modification Action subunit, if the modified message header field comprises a Drop mark, the message header field is directly discarded, and the rest fields corresponding to the message header field and stored in the message buffer PacketBuffer unit are emptied. And if the modified message header field does not carry a Drop mark, packaging the residual field and the message header field from the residual field in the packet buffer unit, and sending the packaged message to a message sending TX unit.

If the packaged message carries a sending CPU mark, the message sending TX unit sends the packaged message to a CPU through a direct memory access unit; and if the packaged message carries the FW mark, the message sending TX unit sends the packaged message to corresponding equipment through a message outlet carried in the packaged message.

In the embodiment of the invention, after the FPGA sends the message with the missed source MAC address to the CPU, the message receiving and sending unit in the CPU receives the message and sends the message to the main management unit, the main management unit forwards the message to the message source MAC address learning unit for learning, the table items learned and generated by the message source MAC address learning unit are sent to the main management unit, the main management unit stores the table items in the memory and generates table item configuration information, and the table item configuration information is sent to the second table item configuration unit in the FPGA through the first table item configuration unit.

The second table item configuration unit forwards the table item configuration information to the Hash table item management Hash table meng subunit, and the Hash table item management Hash table meng subunit can manage the Hash table item configuration table items for the Hash table item management Hash table subunit according to the table item configuration information.

In summary, the message processing device is a device based on a CPU + FPGA heterogeneous system, where the CPU is configured to control and manage functions of the FPGA and the FPGA is configured to specifically process and forward a message, and the CPU and the FPGA cooperatively work to implement processing of a general network message, so as to meet requirements of application scenarios such as network message processing algorithm verification and network protocol offload implementation.

Referring to fig. 4, based on the same inventive concept, an embodiment of the present invention provides a message processing method, where the method is applied to a message processing device, where the message processing device includes a CPU and at least one FPGA, and the method includes:

step 401: at least one FPGA receives table item configuration information of table items configured for the FPGA by a CPU; the table item configuration information carries the storage address of the table item;

step 402: at least one FPGA receives the table item configuration information and the message to be processed, intercepts the message header field of the message to be processed, extracts keywords for table lookup from the message header field, performs table lookup according to the keywords and the table items stored in the storage address, processes the message to be processed according to the table lookup result, and sends the processed message to the device corresponding to the processed message; wherein the key corresponds to the table entry stored by the storage address.

An embodiment of the present invention further provides a message processing system, where the message processing system includes a CPU and at least one FPGA; any one of the at least one FPGA may be, for example, an FPGA in the embodiment shown in fig. 2, and the CPU may be, for example, a CPU in the embodiment shown in fig. 2. Specifically, the FPGA can be used to process the message, and the CPU can schedule each functional unit included in the FPGA, and set and manage parameters of each functional unit, so as to control a process of processing the message by the FPGA.

In the embodiment of the present invention, each functional unit in the CPU may be based on Thread, and then the implementation of the functional unit in the CPU may be Thread code written by C + +; each functional unit in the FPGA may be Kernel-based, and thus, each functional unit in the FPGA may be implemented by a Kernel code written in an OpenCL language. After the codes on the two sides are written, the Kernel codes can be compiled through an OpenCL compiler, the Thread codes can be compiled through a GCC compiler, the compiled Kernel codes are burned into the FPGA, and the Thread codes are loaded through a CPU, so that the functions are realized.

In the embodiments of the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the described unit or division of units is only one division of logical functions, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical or other form.

The functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be an independent physical module.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, all or part of the technical solutions of the embodiments of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device, such as a personal computer, a server, or a network device, or a processor (processor) to execute all or part of the steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a Universal Serial Bus flash drive (usb flash drive), a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, and an optical disk.

The above embodiments are only used to describe the technical solutions of the present application in detail, but the above embodiments are only used to help understanding the method of the embodiments of the present invention, and should not be construed as limiting the embodiments of the present invention. Variations or substitutions that may be readily apparent to one skilled in the art are intended to be included within the scope of the embodiments of the present invention.

Claims

1. A message processing device is characterized by comprising a Central Processing Unit (CPU) and at least one Field Programmable Gate Array (FPGA);

the CPU is used for configuring table entries for the at least one FPGA and sending table entry configuration information for configuring the table entries to the at least one FPGA; the table item configuration information carries the storage address of the table item;

2. The device of claim 1, wherein any one of the at least one FPGA comprises a plurality of functional units, the plurality of functional units specifically comprising:

a message receiving RX unit, configured to receive a message to be processed;

a packet splitting Decap unit, configured to intercept a packet header field of the to-be-processed packet, and send other fields except the packet header field in the to-be-processed packet to packet cache packet buffers in the multiple functional units for storage;

3. The apparatus of claim 2, wherein the lookup engine unit comprises at least one lookup engine, and each lookup engine comprises:

4. The apparatus of claim 3, wherein each lookup engine further comprises:

5. The apparatus of claim 4, wherein the CPU includes a master management Host Main unit and a first control unit, the plurality of functional units further includes a second control unit,

6. The apparatus of claim 3, wherein the CPU further comprises a messaging unit; the plurality of functional units further comprise a direct memory access unit, and the direct memory access unit is connected with the message receiving RX unit and the message sending TX unit;

7. The apparatus of claim 5, wherein the CPU further comprises a first entry configuration unit; the plurality of function units further comprise a second table item configuration unit, and the second table item configuration unit is connected with the table item management tablemsng subunit in each table look-up engine;

and the second table item configuration unit is configured to receive the table item configuration information, and forward the table item configuration information to a table item management tablemsng subunit corresponding to the type according to the type of the table item configured by the table item configuration information.

8. The apparatus of claim 6, wherein any one of the at least one FPGA further comprises:

the message transmission channel is used for transmitting messages;

a req/ack signal path for transmitting a req/ack signal;

9. A message processing method is characterized in that the method is applied to message processing equipment, and the message processing equipment comprises a CPU and at least one FPGA; the method comprises the following steps:

10. The method according to claim 9, wherein the at least one FPGA performs table lookup according to the keyword and the table entry stored in the storage address, and processes the packet to be processed according to a table lookup result, including: