CN107889340A - A kind of dynamic compensation method of impedance line - Google Patents
A kind of dynamic compensation method of impedance line Download PDFInfo
- Publication number
- CN107889340A CN107889340A CN201710920297.7A CN201710920297A CN107889340A CN 107889340 A CN107889340 A CN 107889340A CN 201710920297 A CN201710920297 A CN 201710920297A CN 107889340 A CN107889340 A CN 107889340A
- Authority
- CN
- China
- Prior art keywords
- line
- impedance
- minimum
- offset
- pad position
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000005530 etching Methods 0.000 abstract description 9
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000012797 qualification Methods 0.000 abstract description 4
- 239000003337 fertilizer Substances 0.000 abstract description 3
- 230000007812 deficiency Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
The present invention relates to art of printed circuit boards, specially a kind of dynamic compensation method of impedance line, when being whole plate minimum line or minimum pad position at the compensation that etching is cut down, by the offset of impedance line is modified to the offset consistent with minimum line or minimum pad position in unit and in impedance strip, solve the problems, such as minimum line line width limit on the lower side or minimum pad position dimension width limit on the lower side caused by dynamic compensates and impedance line line fertilizer causes impedance value relatively low.The qualification rate of impedance after etching is improved, substantially increases production efficiency, while reduce quality scrap cost.
Description
Technical field
The present invention relates to art of printed circuit boards, more particularly to a kind of dynamic compensation method of impedance line.
Background technology
At present, in designed lines plate, the dynamic compensation method of impedance line typically uses the dynamic same with common line
Compensation method is supplemented, and step is probably as follows：First all circuits and PAD (containing impedance line) are carried out by same normal compensation values
Compensate pre- big, then for being finely adjusted at portion gap deficiency, then suitably reduce the compensation at this to meet that minimum clearance will
Ask.The great advantage of dynamic compensation is：It can find and solve portion gap deficiency, ensure with copper to be etched thickness relatively
The gap answered.
Usually, the local wired between line, between line and PAD and between PAD and PAD of gap deficiency is produced.Gap deficiency
Place is also tended at the line width for minimum line (or the wide places of minimum PAD), and wiring board is being designed and produced into after Mobile state compensation, gap energy
Requirement is satisfied, but line width (or PAD is wide) offset of minimum line is less than normal compared with the offset of All other routes at this, because
Situations below occurs in this：When whole plate etches, the etch quantity of plate face copper to be etched is substantially uniform consistent, when most after etching
When the line width (or PAD is wide) of small line reaches most lower limit, the impedance line in impedance strip in unit is due to compensated in advance, so compared with this most
The line width of small line easily partially in, the upper limit even exceed the upper limit；Accordingly, during testing impedance, impedance line in unit and in impedance strip
Impedance value is easily relatively low or super lower limit, it is impossible to meet requirement of the client to impedance value.So shortcoming exists when being compensated using dynamic
In：Can cause minimum line (or PAD) compensation with unit in and impedance strip on impedance line line width compensate it is asynchronous, cause impedance line
Impedance value production when be difficult to control.
The content of the invention
The present invention a kind of compensates the offset of minimum pad position or the offset of minimum line in view of the above-mentioned problems, providing
Each impedance line to solve that minimum line line width is less than normal and the dynamic compensation method of impedance line that impedance value is relatively low.
To achieve the above object, the present invention uses following technical scheme：
A kind of dynamic compensation method of impedance line, comprises the following steps：
S1, the theoretical line width that each impedance line is calculated as required and/or pad position theoretical size；
S2, the offset for calculating minimum pad position and/or minimum line offset；
S3, according to the offset of minimum pad position or the offset of minimum line compensate remaining impedance line.
Further, in the step S2, during a width of 0.12mm of minimum pad position, the offset of minimum pad position is
0.01mm。
Further, the offset of impedance line is adjusted to 0.01mm.
Compared with prior art, the beneficial effects of the invention are as follows：The present invention is minimum for whole plate at the compensation that etching is cut down
When line or minimum pad position, by the offset of impedance line is modified to and minimum line or minimum pad position one in unit and in impedance strip
The offset of cause, solve because dynamic compensate caused by minimum line line width it is on the lower side limit or minimum pad position dimension width it is on the lower side limit and
The problem of impedance line line fertilizer causes impedance value relatively low.The qualification rate of impedance after etching is improved, substantially increases production efficiency, together
When reduce quality scrap cost.
Embodiment
In order to more fully understand the technology contents of the present invention, with reference to specific embodiment to technical scheme
It is described further and illustrates.
Embodiment
The present invention provides a kind of dynamic compensation method of impedance line, specific to mend by taking a width of 0.12mm minimums pad position as an example
It is as follows to repay step：
S1, the theoretical size that pad position is calculated as required；
S2, the offset for calculating minimum pad position, during a width of 0.12mm of minimum pad position, the offset of minimum pad position
For 0.01mm, now, impedance line is 0.03mm by the offset normally calculated.
S3, the offset compensating impedance line according to minimum pad position, impedance line offset is reduced to 0.01mm, makes impedance
Line offset is consistent with the offset of minimum pad position, so when pad size reaches requirement after etching, impedance line also meets
Design requirement.
Compensation method contrast after compensation method and change before change is as follows：
If compensated according to original calculate, after the etching the size limit on the lower side of the minimum pad position, and impedance line is due to reason
It is more than the offset of minimum pad position by offset, causes the super upper limit of impedance line line width, corresponding impedance value also super lower limit.
When the present invention is whole plate minimum line or minimum pad position at the compensation that etching is cut down, by unit and in impedance strip
The circuit of impedance line is modified to the offset consistent with minimum line or minimum pad position, solves minimum caused by dynamic compensates
Line line width limit on the lower side or minimum pad position dimension width limit on the lower side and impedance line line fertilizer the problem of causing impedance value relatively low.Use original
When carrying out old dynamic compensation method, impedance qualification rate 10% after etching, scrappage 3%；After new dynamic compensation method, erosion
Impedance qualification rate 95% after quarter, scrappage 0%, substantially increases production efficiency, while reduces quality scrap cost.
The technology contents described above that the present invention is only further illustrated with embodiment, in order to which reader is easier to understand,
But embodiments of the present invention are not represented and are only limitted to this, any technology done according to the present invention extends or recreation, is sent out by this
Bright protection.
Claims (3)
1. a kind of dynamic compensation method of impedance line, it is characterised in that comprise the following steps：
S1, the theoretical line width that each impedance line is calculated as required and/or pad position theoretical size；
S2, the offset for calculating minimum pad position and/or minimum line offset；
S3, according to the offset of minimum pad position or the offset of minimum line compensate remaining impedance line.
2. the dynamic compensation method of impedance line according to claim 1, it is characterised in that：It is minimum in the step S2
During a width of 0.12mm of pad position, the offset of minimum pad position is 0.01mm.
3. the dynamic compensation method of impedance line according to claim 2, it is characterised in that：The offset of impedance line is adjusted
For 0.01mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710920297.7A CN107889340A (en) | 2017-09-30 | 2017-09-30 | A kind of dynamic compensation method of impedance line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710920297.7A CN107889340A (en) | 2017-09-30 | 2017-09-30 | A kind of dynamic compensation method of impedance line |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107889340A true CN107889340A (en) | 2018-04-06 |
Family
ID=61781069
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710920297.7A Pending CN107889340A (en) | 2017-09-30 | 2017-09-30 | A kind of dynamic compensation method of impedance line |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107889340A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030084511A (en) * | 2002-04-27 | 2003-11-01 | 삼성전자주식회사 | The semiconductor memory module comprising the method of compensating the loading effect of tie bar |
| US20040119549A1 (en) * | 2001-12-14 | 2004-06-24 | Nguyen Hung Thai | Cross talk compensation circuit |
| CN104470212A (en) * | 2013-09-25 | 2015-03-25 | 珠海方正科技高密电子有限公司 | A circuit board impedance line compensation method and device |
| CN105120599B (en) * | 2015-09-08 | 2018-01-30 | 广州兴森快捷电路科技有限公司 | A kind of impedance adjustment of the isolated line of wiring board |
-
2017
- 2017-09-30 CN CN201710920297.7A patent/CN107889340A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040119549A1 (en) * | 2001-12-14 | 2004-06-24 | Nguyen Hung Thai | Cross talk compensation circuit |
| KR20030084511A (en) * | 2002-04-27 | 2003-11-01 | 삼성전자주식회사 | The semiconductor memory module comprising the method of compensating the loading effect of tie bar |
| CN104470212A (en) * | 2013-09-25 | 2015-03-25 | 珠海方正科技高密电子有限公司 | A circuit board impedance line compensation method and device |
| CN105120599B (en) * | 2015-09-08 | 2018-01-30 | 广州兴森快捷电路科技有限公司 | A kind of impedance adjustment of the isolated line of wiring board |
Non-Patent Citations (1)
| Title |
|---|
| 奈何桥边的走廊: "阻抗设计指引", 《百度文库》 * |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180406 |
|
| RJ01 | Rejection of invention patent application after publication |