CN107068825B - High-voltage flip-chip LED chip structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a high-voltage flip-chip LED chip structure and a manufacturing method thereof, comprising: a growth substrate deposited with a GaN epitaxial layer; ion implantation to form a plurality of isolation regions, so that the GaN epitaxial layer forms a plurality of mutually independent chips Unit, then perform mesa step etching to form a transparent electrode transmission layer; form a DBR layer; form an interconnect metal layer; form an insulating layer; make N and P electrode pads, etc. The high-voltage flip-chip LED chip of the present invention forms multiple isolation regions by performing ion implantation in the GaN epitaxial layer, which can greatly reduce the loss of the light-emitting area of the light-emitting diode caused by etching, and utilizes the isolation regions formed by ion implantation to make the chip The bridging between the chips can be smoother, and it is easier to bridge between the chips; in addition, the height difference between the chip isolation area and other areas is small, the N and P electrode pads are not easy to conduct, the insulation effect is good, and the yield rate is high when the chip is packaged. Reduce the difficulty of the packaging process, and have stronger compatibility with the packaging bracket.

Description

High-voltage flip-chip LED chip structure and manufacturing method thereof

technical field

The invention belongs to the field of semiconductor lighting and relates to an LED chip structure and a manufacturing method thereof, in particular to a high-voltage flip-chip LED chip structure and a manufacturing method thereof.

Background technique

A light emitting diode (Light Emitting Diode, referred to as LED) is a semiconductor solid-state light-emitting device, which is made by using the principle of semiconductor P-N junction electroluminescence. LED devices have good photoelectric properties such as low turn-on voltage, small size, fast response, good stability, long life, and no pollution. Therefore, they are widely used in outdoor and indoor lighting, backlighting, display, traffic indication and other fields.

There are three types of LED chip structures, namely horizontal structure (front mounted chip), vertical structure (vertical structure chip) and flip chip structure (flip chip); the flip chip structure means that the P and N electrodes of the chip are on the same side of GaN, and the quantum well The emitted light mainly escapes through the transparent sapphire surface. There is no problem of shading the front-mounted chip and vertical chip electrodes and gold wires on the package. The current is directly injected through the metal of the reflective layer. The current distribution is uniform, and the voltage is low and the brightness is high. It is suitable for high power and large The use of chips with current density, flip chip products have the advantages of no wire bonding, low voltage, high light efficiency, low thermal resistance, high reliability, high saturation current density, etc., and have gradually become the key development direction of the market.

In the prior art, the GaN epitaxial layer is usually etched by a dry etching method to form a trench isolation region 3, and the trench isolation region 3 is used to isolate chips, and the formed LED chip structure is shown in FIG. 1 . This method of forming trench isolation regions to isolate adjacent chip units has the following problems:

1. If the GaN epitaxial layer in the isolation trench area is not etched cleanly, it will cause leakage;

2. The long-term dry etching will damage the side wall of the GaN epitaxial layer, which will affect the performance of the chip;

3. During the metal connection between chip units, metal fracture may occur at the groove connection, resulting in poor chip contact;

4. During flip-chip packaging, the solder paste may seep into the isolation trench area, resulting in direct conduction between the N pad and the P pad of the chip, and the packaged device will directly fail. In addition, the solder paste that has penetrated into the isolation trench area may further Seep into a single chip through the side wall, causing leakage;

5. If the width of the deep etching groove is too wide, the light-emitting area will be lost.

In view of the above problems, the present invention provides a new high-voltage flip-chip LED chip structure and manufacturing method thereof, which is a problem to be solved by those skilled in the art. In addition, in this case, the DBR structure is used to replace the metal reflector structure, which solves the metal migration and oxidation of the metal reflector due to changes in the external environment, thereby greatly improving the reliability and reflection efficiency of the LED chip.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a new high-voltage flip-chip LED chip structure and its manufacturing method, which is used to solve the problem that trenches are used as isolation regions in the prior art, and trench connections are prone to occur. Problems such as metal breakage, leakage between chip units, and light-emitting area caused by too wide trench width. In addition, in this case, the DBR structure is used instead of the metal reflector structure, which solves the problem that the metal reflector in the prior art is affected by changes in the external environment. The resulting problems of metal migration and oxidation greatly improve the reliability and reflection efficiency of the LED chip.

In order to achieve the above purpose and other related purposes, the present invention provides a method for manufacturing a high-voltage flip-chip LED chip, which at least includes:

1) Provide a growth substrate with a GaN epitaxial layer deposited on the surface, the GaN epitaxial layer including an N-type GaN layer, a multiple quantum well layer grown on the surface of the N-type GaN layer, and a multi-quantum well layer grown on the surface of the multiple quantum well layer P-type GaN layer;

2) performing ion implantation in the GaN epitaxial layer to form a plurality of isolation regions with flat surfaces, so that the GaN epitaxial layer forms a plurality of mutually independent chip units;

3) etching the GaN epitaxial layer to form an opening exposing the N-type GaN layer;

4) forming a transparent electrode transport layer on the surface of the P-type GaN layer;

5) Covering the surface of the structure obtained in step 4) with a DBR layer, opening holes on the surface of the DBR layer in the opening to expose the N-type GaN layer, and simultaneously opening holes on the surface of the DBR layer to form the exposed The interconnection window of the P-type GaN layer is used to draw out the electrical properties of the P-type GaN layer;

6) preparing a metal connection layer on the surface of the DBR layer, the opening and the interconnection window, so that the P-type GaN layer of the adjacent chip unit is connected to the N-type GaN layer to form a series structure;

7) covering the surface of the DBR layer and the metal connection layer with an insulating layer, and forming an N electrode contact hole and a P electrode contact hole on the insulating layer on the surface of the chip unit;

8) Prepare an N electrode pad in the N electrode contact hole and on the surface of the insulating layer, and prepare a P electrode pad in the P electrode contact hole and on the surface of the insulating layer, and the N electrode pad and the P electrode pad cover at least one of said isolation regions.

As an optimized solution of the method for manufacturing a high-voltage flip-chip LED chip of the present invention, the width of the isolation region formed by ion implantation ranges from 1 to 20 μm.

As an optimized solution of the manufacturing method of the high-voltage flip-chip LED chip of the present invention, the width range of the isolation region formed by ion implantation is 5-10 μm.

As an optimized solution of the manufacturing method of the high-voltage flip-chip LED chip of the present invention, the ion-implanted elements are selected from one or more combinations of P, He, Ar, N, O, H or Fe.

As an optimized solution of the manufacturing method of the high-voltage flip-chip LED chip of the present invention, the ion implantation concentration ranges from 1.0×10 ¹¹ cm ⁻² to 1.0×10 ¹⁶ cm ⁻² .

As an optimized solution of the manufacturing method of the high-voltage flip-chip LED chip of the present invention, the transparent electrode transmission layer is ITO or ZnO.

As an optimized solution of the manufacturing method of the high-voltage flip-chip LED chip of the present invention, the material of the DBR layer is a stack structure formed by superposition of SiO ₂ and Ti ₃ O ₅ or a stack structure formed by superposition of SiO ₂ and TiO ₂ .

As an optimized solution of the manufacturing method of the high-voltage flip-chip LED chip of the present invention, the material of the insulating layer is silicon nitride or silicon dioxide.

The present invention also provides a high-voltage flip-chip LED chip structure, which is prepared by the above preparation method. The chip structure includes: a growth substrate, a GaN epitaxial layer, an isolation region, a transparent electrode transmission layer, a DBR layer, a metal connection layer, an insulating layer, a P electrode pad and an N electrode pad;

The GaN epitaxial layer is deposited on the surface of the growth substrate, and the GaN epitaxial layer includes an N-type GaN layer, a multi-quantum well layer grown on the surface of the N-type GaN layer, and a multi-quantum well layer grown on the surface of the multi-quantum well layer. P-type GaN layer;

The ion implantation of the isolation region is formed in the GaN epitaxial layer;

An opening exposing the N-type GaN layer is formed in the GaN epitaxial layer;

The transparent electrode transport layer is formed on the surface of the P-type GaN layer;

The DBR layer covers the surface of the GaN epitaxial layer and the transparent electrode transport layer, and is formed in the DBR layer to expose the opening of the N-type GaN layer and the interconnection window exposing the P-type GaN layer;

The metal connection layer is formed on the surface of the DBR layer, openings and interconnection windows, so that the P-type GaN layer and the N-type GaN layer of adjacent chip units are connected to form a series structure;

The insulating layer covers the surface of the DBR layer and the metal connection layer, and an N electrode contact hole and a P electrode contact hole are respectively formed in the insulating layer on the surface of the chip unit;

The N electrode pad is prepared in the N electrode contact hole and the surface of the insulating layer, the P electrode pad is prepared in the P electrode contact hole and the surface of the insulating layer, and the N electrode pad and the P electrode are welded together. A disc covers at least one of said isolated areas.

As mentioned above, the high-voltage flip-chip LED chip structure and its manufacturing method of the present invention have the following beneficial effects:

1. Compared with the isolation trench formed by deep etching, the isolation region formed by the ion implantation of the present invention can greatly reduce the loss of the light-emitting area of the light-emitting diode caused by etching. The etching width is generally above 20um, which is too wide. The width of the isolation region formed by ion implantation can be adjusted within a suitable range according to actual design requirements.

2. Adopting the isolation area of the present invention, since the surface of the isolation area is very flat, the bridging between chips can be more gentle, and it is easier to bridge between chips;

3. The height difference between the chip isolation area and other areas of the present invention is small, the insulation effect of the isolation area is good, the yield rate of the chip packaging is high, the difficulty of the packaging process is reduced, and the compatibility with the packaging bracket is stronger.

4. Compared with filling the silicon oxide in the deeply etched trench as chip isolation, the VF4 (lower voltage of 1uA) of the ion-implanted isolation region of the present invention is better.

5. The DBR layer is used as the reflector in the present invention, which can avoid the metal migration and oxidation of the metal reflector in the prior art due to changes in the external environment, thereby greatly improving the reliability and reflection efficiency of the LED chip.

Description of drawings

FIG. 1 is a schematic structural diagram of a high-voltage flip-chip LED chip in the prior art.

2 to 9 are structural flow charts of the method for manufacturing a high-voltage flip-chip LED chip according to the present invention.

Component designation description

1 Growth substrate

2 GaN epitaxial layer

21 N-type GaN layer

22 Multi-quantum well layer and P-type GaN layer

3 Quarantine

4 openings

5 Transparent electrode transport layer

7 DBR layers

8 Interconnect windows

9 Metal connection layer

10 insulating layer

11 N electrode contact hole

12 P electrode contact holes

13 N electrode pad

14 P electrode pad

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to attached picture. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

The invention provides a method for manufacturing a high-voltage flip-chip LED chip. The method at least includes the following steps:

First perform step 1), as shown in FIG. 2 , provide a growth substrate 1 with a GaN epitaxial layer 2 deposited on its surface. A quantum well layer and a P-type GaN layer 22 grown on the surface of the multi-quantum well layer.

In step 1), the growth substrate 1 can be a low thermal conductivity substrate such as a sapphire substrate, and of course, according to process requirements, it can also be other suitable substrates for making LED chips, such as spinel (MgAl ₂ O ₄ ), SiC, ZnS, ZnO or GaAs substrates, etc., are not limited here. The growth substrate 1 in this embodiment is preferably a sapphire substrate.

The process of depositing the N-type GaN layer 21 , the multi-quantum well layer and the P-type GaN layer 22 is a conventional process, which will not be repeated here.

Next, step 2) is performed. As shown in FIG. 3 , ion implantation is performed in the GaN epitaxial layer 2 to form a plurality of flat isolation regions 3 , so that the GaN epitaxial layer 2 forms a plurality of mutually independent chip units.

In step 2), ion implantation is performed on the specified GaN epitaxial layer 2 region through the mask plate design, and the energy and implantation angle required for ion implantation are adjusted according to the thickness of the GaN epitaxial layer 2, so that the isolation region 3 It runs through the entire GaN epitaxial layer, thereby playing an isolation role.

As an example, one or more ions of P, He, Ar, N, O, H or Fe are used for ion implantation to form the plurality of isolation regions 3 in the GaN epitaxial layer. The concentration of the ion implantation is selected within the range of 1.0×10 ¹¹ cm ⁻² to 1.0×10 ¹⁶ cm ⁻² , so that the formed isolation region 3 plays an isolation role.

As an example, the width of the isolation region 3 formed by ion implantation ranges from 1 to 20 μm. Preferably, the isolation region formed by ion implantation has a width in the range of 5-10 μm. For example, the width of the isolation region may be 5 μm, 8 μm, 15 μm, 18 μm and so on. In the prior art, as shown in FIG. 1, an etching process is used to form a trench isolation region 3 in the GaN epitaxial layer to isolate chip units, and the width of the trench formed by etching is generally more than 20 μm, and the width is too wide to cause light-emitting diodes The light-emitting area loss, and the present application can use ion implantation to form the isolation region 3 according to the actual design requirements, and the width is small, which can greatly reduce the loss of the light-emitting area of the light-emitting diode caused by etching. In addition, since the isolation region formed by ion implantation is very flat, the metal connection layer, the P electrode pad and the N electrode pad formed in subsequent preparations, and the parts covering the isolation region are not easy to break.

Step 3) is then performed, as shown in FIG. 4 , etching the GaN epitaxial layer 2 to form an opening 4 exposing the N-type GaN layer 21 .

As shown in FIG. 4, each independent chip can be etched by dry etching or wet etching process, and a penetrating P-type GaN layer 22, a multi-quantum well layer and an N-type GaN layer are formed on the surface of each chip. 21 openings 4 on the surface.

In this embodiment, a dry etching process, such as ICP or PIE process, is used for etching to form the opening 4 exposing the N-type GaN layer 21 .

Then step 4) is executed, as shown in FIG. 5 , a transparent electrode transmission layer 5 is formed on the surface of the P-type GaN layer 22 .

The transparent electrode transmission layer 5 can be formed on the surface of the P-type GaN layer 22 by using evaporation and negative resist lift-off technology or evaporation and etching technology. The transparent electrode transport layer 5 is made of ITO or ZnO.

Step 5) is executed again, as shown in FIG. 6, the surface of the structure obtained in step 4) covers the DBR layer 7, and the surface of the DBR layer 7 is opened in the opening 4, exposing the N-type GaN layer 21, At the same time, holes are opened on the surface of the DBR layer 7 to form an interconnection window 8 exposing the P-type GaN layer 21 , so as to lead out the electrical properties of the P-type GaN layer 22 .

The DBR layer 7 is a stacked structure formed by stacking SiO ₂ and Ti ₃ O ₅ , or a stacked structure formed by stacking SiO ₂ and TiO ₂ , or the like. In this embodiment, the DBR layer 7 is a stacked structure formed by stacking SiO ₂ and TiO ₂ .

It should be noted that the DBR layer formed in the flip chip of the present invention can not only function as a reflector, but also function as an insulation. Using the DBR layer as a reflector can solve the problem of metal migration and oxidation of the metal reflector due to changes in the external environment, thereby greatly improving the reliability and reflection efficiency of the LED chip.

Then perform step 6), as shown in Figure 7, prepare the metal connection layer 9 in the surface of the DBR layer 7, the opening 4 and the interconnection window 8, so that the P-type GaN layer 22 of the adjacent chip unit and the N-type GaN Layers 21 are connected to form a series structure.

The material of the metal connection layer 9 is a combination of one or more of Cr, Al, Ti, Ni, Pt or Au, and the thickness range is

Since the region formed by ion implantation is used as the isolation region 3 of the chip unit, the surface of the isolation region 3 is at the same height as the surface of the GaN epitaxial layer, and when the metal connection layer 9 is used for electrical connection, the bridge between the chip units is smoother , reducing the risk of metal connection layer 9 breaking.

Continue to perform step 7), as shown in Figure 8, cover the insulating layer 10 on the surface of the DBR layer 7 and the metal connection layer 9, and form the N electrode contact hole 11 and the P electrode contact respectively on the insulating layer 10 on the chip unit surface hole 12.

The insulating layer 10 is selected from SiO ₂ or Si ₃ N4 and the like. In this embodiment, the insulating layer 10 is made of SiO ₂ material.

The shape and size of the N electrode contact hole 11 and the P electrode contact hole 12 are not limited. The N-electrode contact hole 11 is used to electrically extract the N-type GaN layer 21 , and the P-electrode contact hole 12 is used to electrically extract the P-type GaN layer 22 .

Finally perform step 8), as shown in Figure 9, prepare N electrode pad 13 in described N electrode contact hole 11 and insulating layer 10 surface, prepare P electrode in described P electrode contact hole 12 and insulating layer 10 surface The pad 14, the N electrode pad 13 and the P electrode pad 14 cover at least one of the isolation regions.

Since there is almost no height difference between the chip isolation area 3 and other areas, the insulation effect of the isolation area is good, and the yield rate of the chip packaging is also greatly improved, thereby reducing the difficulty of the packaging process and having stronger compatibility with the packaging bracket.

As shown in FIG. 9, the N electrode pad 13 and the P electrode pad 14 cover 2 to 3 isolation regions 3. Since the isolation regions 3 are very flat, the use of the isolation regions 3 can well avoid the deep Trench leakage problem.

As shown in Figure 9, the present invention also provides a high-voltage flip-chip LED chip structure, which at least includes: a growth substrate 1, a GaN epitaxial layer 2, an isolation region 3, a transparent electrode transmission layer 5, a DBR layer 7, Metal connection layer 9 , insulating layer 10 , P electrode pad 14 and N electrode pad 13 .

The GaN epitaxial layer 2 is deposited on the surface of the growth substrate 1, and the GaN epitaxial layer includes an N-type GaN layer 21, a multi-quantum well layer grown on the surface of the N-type GaN layer 21, and a multi-quantum well layer grown on the multi-quantum well layer. P-type GaN layer 22 on the surface of the well layer.

The isolation region 3 is formed in the GaN epitaxial layer 2 by ion implantation. As an example, the width of the isolation region 3 formed by ion implantation ranges from 1 to 20 μm. Preferably, the isolation region 3 formed by ion implantation has a width in the range of 5-10 μm.

An opening 4 exposing the N-type GaN layer 21 is formed in the GaN epitaxial layer 2, and the transparent electrode transfer layer 5 is formed on the surface of the P-type GaN layer 22; the DBR layer 7 covers the GaN epitaxial layer 2 and the surface of the transparent electrode transfer layer 5, and are formed in the DBR layer 7 in the opening exposing the N-type GaN layer 21 and the interconnection window 8 exposing the P-type GaN layer; the metal connection layer 9 is formed on the surface of the DBR layer 7, the opening 4 and the interconnection window 8, so that the P-type GaN layer 22 of the adjacent chip unit is connected to the N-type GaN layer 21 to form a series structure; the insulating layer 10 covers the The surface of the DBR layer 7 and the metal connection layer 9, and respectively form an N electrode contact hole 11 and a P electrode contact hole 12 on the insulating layer 10 on the surface of the chip unit; the N electrode pad 13 is prepared in the N electrode contact hole In 11 , the P-electrode pad 14 is prepared in the P-electrode contact hole 12 .

In summary, the present invention provides a high-voltage flip-chip LED chip structure and a manufacturing method thereof, including: a growth substrate deposited with a GaN epitaxial layer; ion implantation to form a plurality of isolation regions, so that the GaN epitaxial layer forms multiple Each independent chip unit, and then perform mesa step etching to form a transparent electrode transmission layer; form a DBR layer; form an interconnect metal layer; form an insulating layer; make N, P electrode pads, etc. The high-voltage flip-chip LED chip of the present invention forms multiple isolation regions by ion implantation in the GaN epitaxial layer, which can greatly reduce the loss of the light-emitting area of the light-emitting diode caused by etching, and utilizes the isolation regions formed by ion implantation to make the chip The bridging between the chips can be smoother, and it is easier to bridge between the chips; in addition, the height difference between the chip isolation area and other areas is small, the N and P electrode pads are not easy to conduct, the insulation effect is good, and the yield rate is high when the chip is packaged. Reduce the difficulty of the packaging process, and have stronger compatibility with the packaging bracket.

Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (9)

1. A manufacturing method of a high-voltage flip-chip LED chip, characterized in that the manufacturing method at least comprises: 1) Provide a growth substrate with a GaN epitaxial layer deposited on the surface, the GaN epitaxial layer including an N-type GaN layer, a multiple quantum well layer grown on the surface of the N-type GaN layer, and a multi-quantum well layer grown on the surface of the multiple quantum well layer P-type GaN layer; 2) performing ion implantation in the GaN epitaxial layer to form a plurality of isolation regions with flat surfaces, so that the GaN epitaxial layer forms a plurality of mutually independent chip units; 3) etching the GaN epitaxial layer to form an opening exposing the N-type GaN layer; 4) forming a transparent electrode transport layer on the surface of the P-type GaN layer; 5) Covering the surface of the structure obtained in step 4) with a DBR layer, opening holes on the surface of the DBR layer in the opening to expose the N-type GaN layer, and simultaneously opening holes on the surface of the DBR layer to form the exposed The interconnection window of the P-type GaN layer is used to lead out the electrical properties of the P-type GaN layer, wherein the DBR layer after opening covers the P-type GaN layer and the transparent electrode transmission layer on it side of 6) preparing a metal connection layer on the surface of the DBR layer, the opening and the interconnection window, so that the P-type GaN layer of the adjacent chip unit is connected to the N-type GaN layer to form a series structure; 7) covering the surface of the DBR layer and the metal connection layer with an insulating layer, and forming an N electrode contact hole and a P electrode contact hole on the insulating layer on the surface of the chip unit; 8) Prepare an N electrode pad in the N electrode contact hole and on the surface of the insulating layer, and prepare a P electrode pad in the P electrode contact hole and on the surface of the insulating layer, and the N electrode pad and the P electrode pad cover at least one of said isolation regions. 2 . The method for manufacturing a high-voltage flip-chip LED chip according to claim 1 , wherein the isolation region formed by ion implantation has a width ranging from 1 to 20 μm. 3 . The method for manufacturing a high-voltage flip-chip LED chip according to claim 2 , wherein the isolation region formed by ion implantation has a width ranging from 5 μm to 10 μm. 4 . 4. The manufacturing method of high-voltage flip-chip LED chips according to claim 1, characterized in that: the ion-implanted elements are selected from one or more of P, He, Ar, N, O, H or Fe The combination. 5 . The method for manufacturing a high-voltage flip-chip LED chip according to claim 1 , wherein the ion implantation concentration ranges from 1.0×10 ¹¹ cm ⁻² to 1.0×10 ¹⁶ cm ⁻² . 6. The manufacturing method of a high-voltage flip-chip LED chip according to claim 1, wherein the transparent electrode transfer layer is ITO or ZnO. 7. The manufacturing method of high-voltage flip-chip LED chips according to claim 1, characterized in that: the material of the DBR layer is a stack structure formed by superposition of SiO ₂ and Ti ₃ O ₅ or a stack formed by superposition of SiO ₂ and TiO ₂ structure. 8. The manufacturing method of a high-voltage flip-chip LED chip according to claim 1, wherein the material of the insulating layer is silicon nitride or silicon dioxide. 9. A high-voltage flip-chip LED chip structure, characterized in that: the chip structure includes: growth substrate, GaN epitaxial layer, isolation region, transparent electrode transmission layer, DBR layer, metal connection layer, insulating layer, P electrode welding plate and N electrode pad; The GaN epitaxial layer is deposited on the surface of the growth substrate, and the GaN epitaxial layer includes an N-type GaN layer, a multi-quantum well layer grown on the surface of the N-type GaN layer, and a multi-quantum well layer grown on the surface of the multi-quantum well layer. P-type GaN layer; The ion implantation of the isolation region is formed in the GaN epitaxial layer; An opening exposing the N-type GaN layer is formed in the GaN epitaxial layer; The transparent electrode transport layer is formed on the surface of the P-type GaN layer; The DBR layer covers the surface of the GaN epitaxial layer and the transparent electrode transport layer, and is formed in the DBR layer in the opening exposing the N-type GaN layer and the interconnection window exposing the P-type GaN layer, Wherein, the DBR layer after opening covers the side of the P-type GaN layer and the transparent electrode transmission layer on it; The metal connection layer is formed on the surface of the DBR layer, openings and interconnection windows, so that the P-type GaN layer and the N-type GaN layer of adjacent chip units are connected to form a series structure; The insulating layer covers the surface of the DBR layer and the metal connection layer, and an N electrode contact hole and a P electrode contact hole are respectively formed in the insulating layer on the surface of the chip unit; The N electrode pad is prepared in the N electrode contact hole and the surface of the insulating layer, the P electrode pad is prepared in the P electrode contact hole and the surface of the insulating layer, and the N electrode pad and the P electrode are welded together. A disc covers at least one of said isolated areas.