CN106887427A - A MOSFET with Integrated Schottky - Google Patents
A MOSFET with Integrated Schottky Download PDFInfo
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Abstract
本发明涉及功率半导体领域，特别涉及一种集成肖特基的MOSFET，包括MOSFET区域以及两个MOSFET区域之间的肖特基区域，所述肖特基区域的N型漂移区上表面中形成两个不连续的第二沟槽，所述两个第二沟槽内、所述第二沟槽上以及两个第二沟槽之间沉积阳极金属，所述阳极金属与所述MOSFET区域的源电极电性连接，所述第二沟槽与其相邻的MOSFET区域的P型掺杂区接触，并且所述第二沟槽深度不大于所述MOSFET区域的P型掺杂区的深度，本发明减小了被集成的肖特基二极管的反向漏电流及其所占芯片的面积。
The present invention relates to the field of power semiconductors, and in particular to a MOSFET with integrated Schottky diodes, comprising a MOSFET region and a Schottky region between two MOSFET regions, wherein two discontinuous second grooves are formed in the upper surface of an N-type drift region of the Schottky region, anode metals are deposited in, on and between the two second grooves, the anode metals are electrically connected to a source electrode of the MOSFET region, the second grooves are in contact with a P-type doping region of an adjacent MOSFET region, and the depth of the second grooves is not greater than the depth of the P-type doping region of the MOSFET region. The present invention reduces the reverse leakage current of an integrated Schottky diode and the area of a chip occupied by the second grooves.
Description
技术领域technical field
本发明涉及功率半导体领域，特别涉及一种集成肖特基的MOSFET。The invention relates to the field of power semiconductors, in particular to a Schottky-integrated MOSFET.
技术背景technical background
功率金属氧化物半导体场效应晶体管(简称功率MOSFET)固有一个与其并联的寄生二极管，寄生二极管的阳极与MOSFET的体区以及源极相连，阴极与MOSFET的漏极相连，因此功率MOSFET常常被用来续流或者钳制电压。A power metal-oxide-semiconductor field-effect transistor (referred to as a power MOSFET) inherently has a parasitic diode connected in parallel with it. The anode of the parasitic diode is connected to the body and source of the MOSFET, and the cathode is connected to the drain of the MOSFET. Therefore, the power MOSFET is often used freewheeling or clamping voltage.
这种寄生二极管与普通二极管一样，由少子参与导电，因此有反向恢复时间，从而降低开关速度、增加开关损耗。肖特基二极管具有较低的正向二极管电压降等优势，通常与MOSFET器件并联，以改善器件开关动作的二极管恢复时间，可抑制器件运行时非开关部分的功率损耗。This kind of parasitic diode is the same as the ordinary diode, and the minority carrier participates in the conduction, so it has a reverse recovery time, thereby reducing the switching speed and increasing the switching loss. Schottky diodes have advantages such as low forward diode voltage drop, and are usually connected in parallel with MOSFET devices to improve the diode recovery time of the switching action of the device, which can suppress the power loss of the non-switching part during device operation.
但是肖特基二极管通常具有很高的反向偏置漏电流，对器件的性能产生不良的影响，同时，现有技术在MOSFET器件中集成肖特基二极管，通常需要较大的芯片面积。However, the Schottky diode usually has a high reverse bias leakage current, which has a bad influence on the performance of the device. Meanwhile, the integration of the Schottky diode in the MOSFET device in the prior art usually requires a larger chip area.
发明内容Contents of the invention
本发明的目的是提供一种集成肖特基的MOSFET，减小被集成的肖特基二极管的反向漏电流及其所占芯片的面积。The object of the present invention is to provide an integrated Schottky MOSFET, which reduces the reverse leakage current of the integrated Schottky diode and the chip area it occupies.
为实现上述目的，本发明采用如下技术方案：To achieve the above object, the present invention adopts the following technical solutions:
一种集成肖特基的MOSFET，包括：MOSFET区域以及两个MOSFET区域之间的肖特基区域，所述MOSFET区域包括自下而上依次层叠的漏电极，N型重掺杂区，N型漂移区，P型掺杂区、N型掺杂区、源电极以及贯穿N型掺杂区和P型掺杂区延伸至N型漂移区内的第一沟槽，所述第一沟槽内填充导电多晶硅，并且所述第一沟槽侧壁以及底部形成栅绝缘层，所述导电多晶硅与源电极间被绝缘介质隔开，相邻两个所述MOSFET区域之间形成肖特基区域，所述肖特基区域的N型漂移区上表面与所述MOSFET区域的N型掺杂区上表面在同一平面，并且所述所述肖特基区域的N型漂移区上表面中形成两个不连续的第二沟槽，所述第二沟槽沟槽侧壁的长度大于沟槽口的宽度，所述两个第二沟槽内、所述第二沟槽上以及两个第二沟槽之间沉积阳极金属，所述阳极金属与所述MOSFET区域的源电极电性连接，所述第二沟槽与其相邻的MOSFET区域的P型掺杂区接触，并且所述第二沟槽深度不大于所述MOSFET区域的P型掺杂区的深度。An integrated Schottky MOSFET, comprising: a MOSFET region and a Schottky region between two MOSFET regions, the MOSFET region includes a drain electrode stacked sequentially from bottom to top, an N-type heavily doped region, an N-type A drift region, a P-type doped region, an N-type doped region, a source electrode, and a first trench extending through the N-type doped region and the P-type doped region into the N-type drift region, the first trench Filling with conductive polysilicon, and forming a gate insulating layer on the sidewall and bottom of the first trench, the conductive polysilicon and the source electrode are separated by an insulating medium, and a Schottky region is formed between two adjacent MOSFET regions, The upper surface of the N-type drift region of the Schottky region is on the same plane as the upper surface of the N-type doped region of the MOSFET region, and two Discontinuous second grooves, the length of the groove sidewall of the second groove is greater than the width of the groove mouth, the inside of the two second grooves, on the second groove and the two second grooves Anode metal is deposited between the grooves, the anode metal is electrically connected to the source electrode of the MOSFET region, the second groove is in contact with the P-type doped region of the adjacent MOSFET region, and the second groove The depth is not greater than the depth of the P-type doped region in the MOSFET region.
优选地，所述MOSFET区域的P型掺杂区与相邻的肖特基区域的所述第二沟槽接触处形成P型重掺杂区。Preferably, the P-type doped region of the MOSFET region is in contact with the second trench of the adjacent Schottky region to form a P-type heavily doped region.
优选地，所述MOSFET区域的P型掺杂区延伸至相邻的肖特基区域的所述第二沟槽底部。Preferably, the P-type doped region of the MOSFET region extends to the bottom of the second trench of the adjacent Schottky region.
优选地，所述MOSFET区域的P型掺杂区包围相邻的肖特基区域的所述第二沟槽整个底部。Preferably, the P-type doped region of the MOSFET region surrounds the entire bottom of the second trench of the adjacent Schottky region.
优选地，所述肖特基区域的两个第二沟槽之间形成P型保护区。Preferably, a P-type protection region is formed between the two second trenches in the Schottky region.
优选地，所述第二沟槽为斜沟槽。Preferably, the second groove is an oblique groove.
优选地，所述MOSFET区域的源电极与所述肖特基区域的阳极金属接触相连。Preferably, the source electrode of the MOSFET region is connected to the anode metal contact of the Schottky region.
优选地，所述MOSFET区域的源电极与所述肖特基区域的阳极金属材料相同。Preferably, the source electrode of the MOSFET region is made of the same metal material as the anode of the Schottky region.
相对于现有技术，本发明具有以下有益效果：Compared with the prior art, the present invention has the following beneficial effects:
本发明集成肖特基的MOSFET，在相邻两个MOSFET区域之间形成的肖特基区域里包括两个不连续的第二沟槽，所述两个第二沟槽内、所述第二沟槽上以及两个第二沟槽之间沉积阳极金属，所述阳极金属与肖特基区域的N型漂移区形成肖特基接触，所以第二沟槽的形成增加了肖特基接触的面积，降低了器件的正向导通电压，反过来，若在同等的正向导通电压的要求下，本发明肖特基区域占据更小的芯片面积。The Schottky-integrated MOSFET of the present invention includes two discontinuous second grooves in the Schottky region formed between two adjacent MOSFET regions. In the two second grooves, the second An anode metal is deposited on the trench and between the two second trenches, and the anode metal forms a Schottky contact with the N-type drift region of the Schottky region, so the formation of the second trench increases the Schottky contact. The area reduces the forward conduction voltage of the device. Conversely, if the same forward conduction voltage is required, the Schottky region of the present invention occupies a smaller chip area.
同时，本发明所述肖特基区域的第二沟槽与其相邻的MOSFET区域的P型掺杂区接触，即P型掺杂区与阳极金属接触，而阳极金属与源电极电性连接，所以一方面P型掺杂区实现作为寄生二极管的阳极区的作用，另一方面，肖特基区域的第二沟槽与其相邻的MOSFET区域的P型掺杂区接触，即肖特基区域的肖特基二极管与MOSFET区域的寄生二极管相连，当MOSFET区域的漏电极电压大于源电极电压(即肖特基区域的阴极电压大于阳极电压)时，肖特基二极管与MOSFET区域的寄生二极管反向偏置，所述肖特基区域的第二沟槽深度不大于所述MOSFET区域的P型掺杂区的深度，MOSFET区域的寄生二极管的PN结反向偏置耗尽对与其相连的肖特结二极管起到保护作用，减小肖特基二极管的反向漏电流。At the same time, the second trench in the Schottky region of the present invention is in contact with the P-type doped region of the adjacent MOSFET region, that is, the P-type doped region is in contact with the anode metal, and the anode metal is electrically connected to the source electrode, Therefore, on the one hand, the P-type doped region functions as the anode region of the parasitic diode; on the other hand, the second groove of the Schottky region is in contact with the P-type doped region of the adjacent MOSFET region, that is, the Schottky region The Schottky diode is connected to the parasitic diode in the MOSFET region. When the drain electrode voltage of the MOSFET region is greater than the source electrode voltage (that is, the cathode voltage of the Schottky region is greater than the anode voltage), the Schottky diode and the parasitic diode of the MOSFET region are reversed. direction bias, the depth of the second trench in the Schottky region is not greater than the depth of the P-type doped region in the MOSFET region, and the reverse bias of the PN junction of the parasitic diode in the MOSFET region depletes the Schottky region connected to it. The special junction diode plays a protective role and reduces the reverse leakage current of the Schottky diode.
附图说明Description of drawings
图1为第一实施例结构示意图；Fig. 1 is a schematic structural view of the first embodiment;
图2为第二实施例结构示意图；Fig. 2 is the structural representation of the second embodiment;
图3为第三实施例结构示意图。Fig. 3 is a schematic structural diagram of the third embodiment.
具体实施方式detailed description
下面结合附图以及实施例对本发明进行介绍，实施例仅用于对本发明进行解释，并不对本发明有任何限定作用。The present invention will be introduced below in conjunction with the accompanying drawings and embodiments, and the embodiments are only used to explain the present invention and do not limit the present invention in any way.
第一实施例first embodiment
如图1所示，本实施例集成肖特基的MOSFET，包括：MOSFET区域100以及两个MOSFET区域100之间的肖特基区域200，所述MOSFET区域100包括自下而上依次层叠的漏电极10，N型重掺杂区20，N型漂移区30，P型掺杂区40、N型掺杂区50、源电极60以及贯穿N型掺杂区50和P型掺杂区60延伸至N型漂移区30内的第一沟槽70，所述第一沟槽70内填充导电多晶硅71，并且所述第一沟槽70侧壁以及底部形成栅绝缘层72，所述导电多晶硅71与源电极60间被绝缘介质73隔开，相邻两个所述MOSFET区域100之间形成肖特基区域200，所述肖特基区域200的N型漂移区30上表面与所述MOSFET区域100的N型掺杂区50上表面在同一平面，并且所述肖特基区域200的N型漂移区30上表面中形成两个不连续的第二沟槽80，所述第二沟槽80沟槽侧壁的长度大于沟槽口的宽度，所述两个第二沟槽80内、所述第二沟槽80上以及两个第二沟槽80之间沉积阳极金属81，所述阳极金属81与所述MOSFET区域100的源电极60电性连接，所述第二沟槽80与其相邻的MOSFET区域100的P型掺杂区40接触，并且所述第二沟槽80深度不大于所述MOSFET区域100的P型掺杂区40的深度。As shown in FIG. 1 , this embodiment integrates Schottky MOSFETs, including: a MOSFET region 100 and a Schottky region 200 between the two MOSFET regions 100, and the MOSFET region 100 includes leakage currents stacked sequentially from bottom to top. Pole 10, N-type heavily doped region 20, N-type drift region 30, P-type doped region 40, N-type doped region 50, source electrode 60 and extending through N-type doped region 50 and P-type doped region 60 To the first trench 70 in the N-type drift region 30, the first trench 70 is filled with conductive polysilicon 71, and the sidewall and bottom of the first trench 70 form a gate insulating layer 72, and the conductive polysilicon 71 Separated from the source electrode 60 by an insulating medium 73, a Schottky region 200 is formed between two adjacent MOSFET regions 100, and the upper surface of the N-type drift region 30 of the Schottky region 200 is in contact with the MOSFET region. The upper surface of the N-type doped region 50 of 100 is on the same plane, and two discontinuous second trenches 80 are formed in the upper surface of the N-type drift region 30 of the Schottky region 200, and the second trenches 80 The length of the side wall of the groove is greater than the width of the groove opening, and an anode metal 81 is deposited in, on, and between the two second grooves 80 in the two second grooves 80, and the anode The metal 81 is electrically connected to the source electrode 60 of the MOSFET region 100, the second trench 80 is in contact with the P-type doped region 40 of the adjacent MOSFET region 100, and the depth of the second trench 80 is not greater than The depth of the P-type doped region 40 of the MOSFET region 100 .
本实施例集成肖特基的MOSFET，在相邻两个MOSFET区域100之间形成的肖特基区域200里包括两个不连续的第二沟槽80，所述两个第二沟槽80内、所述第二沟槽80上以及两个第二沟槽80之间沉积阳极金属81，所述阳极金属81与肖特基区域200的N型漂移区30形成肖特基接触，所以第二沟槽80的形成增加了肖特基接触的面积，降低了器件的正向导通电压，反过来，若在同等的正向导通电压的要求下，本发明肖特基区域占据更小的芯片面积。述第二沟槽80沟槽侧壁的长度大于沟槽口的宽度，加强了第二沟槽80的形成增加了肖特基接触的面积的确定性。This embodiment integrates Schottky MOSFETs, and the Schottky region 200 formed between two adjacent MOSFET regions 100 includes two discontinuous second trenches 80, and the two second trenches 80 1. An anode metal 81 is deposited on the second trench 80 and between the two second trenches 80, and the anode metal 81 forms a Schottky contact with the N-type drift region 30 of the Schottky region 200, so the second The formation of the groove 80 increases the area of the Schottky contact and reduces the forward conduction voltage of the device. Conversely, if the same forward conduction voltage is required, the Schottky region of the present invention occupies a smaller chip area . The length of the trench sidewall of the second trench 80 is greater than the width of the trench opening, which strengthens the formation of the second trench 80 and increases the certainty of the area of the Schottky contact.
同时，本实施例所述肖特基区域200的第二沟槽80与其相邻的MOSFET区域的P型掺杂区40接触，即P型掺杂区40与阳极金属81接触，而阳极金属81与源电极60电性连接，所以一方面P型掺杂区40实现作为寄生二极管的阳极区的作用，另一方面，肖特基区域200的第二沟槽80与其相邻的MOSFET区域100的P型掺杂区40接触，即肖特基区域200的肖特基二极管与MOSFET区域100的寄生二极管相连，当MOSFET区域100的漏电极10电压大于源电极60电压(即肖特基区域200的阴极电压大于阳极电压)时，肖特基二极管与MOSFET区域100的寄生二极管反向偏置，所述肖特基区域200的第二沟槽80深度不大于所述MOSFET区域100的P型掺杂区40的深度，MOSFET区域100的寄生二极管的PN结反向偏置耗尽对与其相连的肖特结二极管起到保护作用，减小肖特基二极管的反向漏电流。本实施例所述MOSFET区域100的源电极60可通过与所述肖特基区域200的阳极金属81接触相连实现电性连接，所述MOSFET区域100的源电极60与所述肖特基区域200的阳极金属81材料也可以相同，此时，源电极60与阳极金属81可同时沉积，简化工艺流程。At the same time, the second trench 80 of the Schottky region 200 in this embodiment is in contact with the P-type doped region 40 of its adjacent MOSFET region, that is, the P-type doped region 40 is in contact with the anode metal 81, and the anode metal 81 It is electrically connected with the source electrode 60, so on the one hand, the P-type doped region 40 realizes the role of the anode region as a parasitic diode; on the other hand, the second trench 80 of the Schottky region 200 and its adjacent MOSFET region 100 The P-type doped region 40 contacts, that is, the Schottky diode in the Schottky region 200 is connected to the parasitic diode in the MOSFET region 100, and when the voltage at the drain electrode 10 of the MOSFET region 100 is greater than the voltage at the source electrode 60 (that is, the voltage at the Schottky region 200 When the cathode voltage is greater than the anode voltage), the Schottky diode and the parasitic diode of the MOSFET region 100 are reverse-biased, and the depth of the second groove 80 of the Schottky region 200 is not greater than the P-type doping of the MOSFET region 100 The depth of the region 40, the reverse bias depletion of the PN junction of the parasitic diode in the MOSFET region 100 protects the Schottky junction diode connected to it, and reduces the reverse leakage current of the Schottky diode. The source electrode 60 of the MOSFET region 100 in this embodiment can be electrically connected by being in contact with the anode metal 81 of the Schottky region 200, and the source electrode 60 of the MOSFET region 100 is connected to the Schottky region 200. The material of the anode metal 81 can also be the same, at this time, the source electrode 60 and the anode metal 81 can be deposited simultaneously, which simplifies the process flow.
本实施例优选地，所述MOSFET区域100的P型掺杂区40与相邻的肖特基区域200的所述第二沟槽80接触处还可以形成P型重掺杂区41，一方面P型重掺杂区41减小P型掺杂区40与阳极金属81的接触电阻，减小功率损耗，另一方面，P型重掺杂区41在肖特基二极管处于反偏状态时，使得PN耗尽层更多向掺杂浓度较小的N型漂移区30扩展，减小肖特结二极管反向漏电流。此外，本实施例所述MOSFET区域100的P型掺杂区40可延伸至相邻的肖特基区域200的所述第二沟槽80底部，加强对肖特基区域反向漏电流的减小，优选地，所述MOSFET区域100的P型掺杂区40包围相邻的肖特基区域200的所述第二沟槽40整个底部，本实施例图1示出此种设置，肖特基二极管处于反向偏置状态时，P型掺杂区40与N型漂移区30形成的PN结耗尽甚至可以连在一起，进一步加强对肖特基区域反向漏电流的减小。In this embodiment, preferably, a P-type heavily doped region 41 may also be formed at the contact between the P-type doped region 40 of the MOSFET region 100 and the second trench 80 of the adjacent Schottky region 200. On the one hand The P-type heavily doped region 41 reduces the contact resistance between the P-type doped region 40 and the anode metal 81, reducing power loss. On the other hand, when the P-type heavily doped region 41 is in the reverse bias state of the Schottky diode, The PN depletion layer expands more to the N-type drift region 30 with a lower doping concentration, reducing the reverse leakage current of the Schott junction diode. In addition, the P-type doped region 40 of the MOSFET region 100 in this embodiment can extend to the bottom of the second trench 80 of the adjacent Schottky region 200, so as to strengthen the reduction of the reverse leakage current of the Schottky region. Small, preferably, the P-type doped region 40 of the MOSFET region 100 surrounds the entire bottom of the second trench 40 of the adjacent Schottky region 200, this embodiment is shown in Figure 1, Schottky When the base diode is in the reverse biased state, the depletion of the PN junction formed by the P-type doped region 40 and the N-type drift region 30 can even be connected together, further strengthening the reduction of the reverse leakage current in the Schottky region.
第二实施例second embodiment
如图2所示，本实施例与第一实施例技术方案基本相同，区别在于，本实施例所述肖特基区域200的两个第二沟槽80之间掺杂形成了P型保护区90，掺杂方式可以通过离子注入掺杂，肖特基二极管处于反向偏置状态时，P型保护区90与N型漂移区30形成PN耗尽，减小反向漏电流，增加反向抗压能力。As shown in Figure 2, the technical solution of this embodiment is basically the same as that of the first embodiment, the difference is that the doping between the two second trenches 80 of the Schottky region 200 described in this embodiment forms a P-type protection region 90. The doping method can be doped by ion implantation. When the Schottky diode is in the reverse bias state, the P-type protection region 90 and the N-type drift region 30 form a PN depletion, which reduces the reverse leakage current and increases the reverse Stress resistance.
第三实施例third embodiment
如图3所示，本实施例与第一实施例技术方案基本相同，区别在于，本实施所述第二沟槽80为斜沟槽，斜沟槽的设置，减轻MOSFET中肖特基二极处于反向偏置状态时，沟槽底角以及顶角处的电场聚集，增加方向耐压能力，减小反向漏电流。As shown in Figure 3, the technical solution of this embodiment is basically the same as that of the first embodiment, the difference is that the second groove 80 in this embodiment is an oblique groove, and the setting of the oblique groove reduces the Schottky diode in MOSFET. In the reverse bias state, the electric field at the bottom corner and the top corner of the trench gathers, which increases the directional withstand voltage capability and reduces the reverse leakage current.
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| CN102088021A (en) * | 2009-12-03 | 2011-06-08 | 达尔科技股份有限公司 | Trench MOS device with Schottky diode and manufacturing method thereof |
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