CN105472602A - Encryption device and encryption method - Google Patents

Abstract

The embodiment of the present invention discloses an encryption device and method; wherein, the encryption method includes: obtaining a first parameter; the first parameter includes: a key, an encryption parameter, a source address, a destination address, and a data length; according to the The key in the first parameter and the encryption parameter generate a key stream; read in the data to be encrypted, process the data to be encrypted and the key stream according to the first encryption method, obtain encrypted data, and output the the encrypted data.

Description

An encryption device and encryption method

technical field

The present invention relates to wireless communication technology, in particular to an encryption device and method.

Background technique

Wireless communication systems are widely used in various types of communications such as voice, video, and data. Computing the integrity of transmitted data is an effective means to protect data security and prevent unauthorized tampering.

In a Long Term Evolution (LTE, Long Term Evolution) communication system, in order to meet high-speed and secure data transmission, an EIA3 integrity algorithm appears.

The EIA3 integrity algorithm is one of the Zu Chongzhi algorithm sets; the Zu Chongzhi algorithm set is an encryption and integrity algorithm independently designed by Chinese scholars, including Zu Chongzhi (ZUC) algorithm, encryption algorithm 128-EEA3 and integrity algorithm 128-EIA3. This set of algorithms has been approved as the third set of algorithms for international encryption and integrity standards for LTE wireless communications.

However, only the algorithm principle and software implementation are proposed in the prior art; and in the practical LTE communication system, the data transmission rate is very high, the calculation process of generating the key stream by the ZUC algorithm is very complicated, and the data needs to be transferred from the memory After the data is read out, the integrity calculation is performed through the generated key stream and data, and then the data is stored in the memory; the whole process cannot be realized by software alone. However, a hardware system capable of supporting ZUC algorithm encryption has not yet been proposed.

Contents of the invention

In order to solve the existing technical problems, the embodiment of the present invention provides an encryption device and method, which can solve the problem that the ZUC algorithm is used for encryption without hardware system support.

In order to achieve the above object, the technical solution of the embodiment of the present invention is achieved in this way:

An embodiment of the present invention provides an encryption device, which includes: a data storage module, a key stream processing module, and an encryption processing module; wherein,

The data storage module is configured to obtain a first parameter, and when a first preset condition is met, send the key and encryption parameters in the first parameter to the key stream processing module; the first parameter Including: key, encryption parameter, source address, destination address and data length; it is also used to read in the data to be encrypted according to the source address and data length in the first parameter, and send the data to be encrypted to the The encryption processing module; also used for receiving the encrypted data sent by the encryption processing module according to the destination address and data length in the first parameter, and outputting the encrypted data;

The key stream processing module is configured to receive the key and encryption parameters in the first parameter sent by the data storage module, generate a key stream according to the key and encryption parameters, and convert the key stream to sent to the encryption processing module;

The encryption processing module is configured to receive the data to be encrypted sent by the data storage module and the key stream sent by the key stream processing module, and convert the data to be encrypted and the key The stream is processed according to the first encryption method to obtain encrypted data, and the encrypted data is sent to the data storage module.

In the above scheme, the data storage module includes: a bus slave processing module, a finite state machine (FSM, FiniteStateMachine) control module, and a bus master processing module; wherein,

The bus slave processing module is used to obtain a first parameter, and send the first parameter to the FSM control module; the first parameter includes: key, encryption parameter, source address, destination address and data length information ;

The FSM control module is configured to send the key and encryption parameters to the key stream processing module when the first preset condition is met according to the first parameter sent by the bus from the processing module, and send the Send the source address, destination address and data length information to the main bus processing module;

The main bus processing module is used to read the data to be encrypted according to the source address and data length information sent by the FSM control module, and send the data to be encrypted to the encryption processing module; Receive the encrypted data sent by the encryption processing module according to the destination address and data length information sent by the FSM control module, and output the encrypted data.

In the above solution, the bus master processing module includes: a first cache module and a second cache module; wherein,

The first cache module is configured to read in the data to be encrypted according to the source address and data length information sent by the FSM control module, and send the data to be encrypted when a second preset condition is met to the encryption processing module;

The second cache module is configured to receive the encrypted data sent by the encryption processing module according to the destination address and data length information sent by the FSM control module, and output the encrypted data when a third preset condition is met. data.

In the above solution, the interface adopted by the bus master processing module includes but is not limited to an AXI master interface or an AHB master interface.

In the above solution, the interface adopted by the bus slave processing module includes but is not limited to an AXI slave interface or an AHB slave interface.

In the above solution, the key stream processing module is configured to generate multiple key streams in parallel according to the key and encryption parameters.

The embodiment of the present invention also provides an encryption method, the method comprising:

Obtain a first parameter; the first parameter includes: a key, an encryption parameter, a source address, a destination address, and a data length;

generating a key stream according to the key and encryption parameters in the first parameter;

Reading in the data to be encrypted, processing the data to be encrypted and the key stream according to a first encryption method to obtain encrypted data, and outputting the encrypted data.

In the above solution, the generating a key stream according to the key and encryption parameters in the first parameter includes: parallelly generating multiple key streams according to the key and encryption parameters in the first parameter.

In the above solution, the acquiring the first parameter includes: acquiring the first parameter by using an AXI master interface or an AHB master interface including but not limited to.

In the above scheme, the reading of the data to be encrypted includes: reading the data to be encrypted by using an AXI master interface or an AHB master interface including but not limited to;

Correspondingly, the outputting the encrypted data includes: outputting the encrypted data by using an AXI master interface or an AHB master interface including but not limited to.

The encryption device and method provided by the embodiments of the present invention, the encryption device includes: a data storage module, a key stream processing module, and an encryption processing module; the data storage module is used to obtain the first parameter, and the first preset is satisfied condition, send the key and encryption parameter in the first parameter to the key stream processing module; the first parameter includes: key, encryption parameter, source address, destination address, and data length; Read in the data to be encrypted according to the source address and data length in the first parameter, and send the data to be encrypted to the encryption processing module; The data length receives the encrypted data sent by the encryption processing module, and outputs the encrypted data; the key stream processing module is used to receive the key and the encryption parameter in the first parameter sent by the data storage module, Generate a key stream according to the key and encryption parameters, and send the key stream to the encryption processing module; the encryption processing module is configured to receive the data to be encrypted and the data to be encrypted sent by the data storage module The key stream sent by the key stream processing module processes the data to be encrypted and the key stream according to a first encryption method to obtain encrypted data, and sends the encrypted data to the data storage module. By adopting the technical solution of the embodiment of the present invention, a hardware system for encrypting by the ZUC algorithm is proposed, which solves the problem that the ZUC algorithm has no hardware system support in the prior art; and, the technical solution provided by the embodiment of the present invention realizes the The high-speed and efficient data processing solves the problem that the original ZUC algorithm has low processing efficiency and is not suitable for hardware system implementation. At the same time, the power consumption is reduced as much as possible, and the data processing speed is greatly improved.

Description of drawings

FIG. 1 is a schematic diagram of a first compositional structure of an encryption device according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a second composition structure of an encryption device according to an embodiment of the present invention;

FIG. 3 is a logical schematic diagram of an initialization process in a key stream generation process in an embodiment of the present invention;

FIG. 4 is a logical schematic diagram of a key stream generation process in an embodiment of the present invention;

FIG. 5 is a schematic flowchart of an encryption method according to an embodiment of the present invention.

detailed description

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

The embodiment of the present invention provides an encryption device; FIG. 1 is a schematic diagram of the first composition structure of the encryption device according to the embodiment of the present invention; as shown in FIG. 1 , the encryption device includes: a data storage module 11, a key stream processing Module 12 and encryption processing module 13; Wherein,

The data storage module 11 is configured to obtain a first parameter, and when a first preset condition is met, send the key and encryption parameters in the first parameter to the key stream processing module 12; the second A parameter includes: a key, an encryption parameter, a source address, a destination address, and a data length; it is also used to read in data to be encrypted according to the source address and data length in the first parameter, and send the data to be encrypted To the encryption processing module 13; also for receiving the encrypted data sent by the encryption processing module 13 according to the destination address and data length in the first parameter, and outputting the encrypted data;

The key stream processing module 12 is configured to receive the key and encryption parameters in the first parameter sent by the data storage module 11, generate a key stream according to the key and encryption parameters, and convert the encryption The key stream is sent to the encryption processing module 13;

The encryption processing module 13 is configured to receive the data to be encrypted sent by the data storage module 11 and the key stream sent by the key stream processing module 12, and convert the data to be encrypted and the The key stream is processed according to the first encryption method to obtain encrypted data, and the encrypted data is sent to the data storage module 11 .

FIG. 2 is a schematic diagram of the second composition structure of the encryption device according to the embodiment of the present invention; as shown in FIG. 2 , specifically, the data storage module includes: a bus slave processing module 111, an FSM control module 112, and a bus master processing module 113 ;in,

The bus slave processing module 111 is configured to obtain a first parameter, and send the first parameter to the FSM control module 112; the first parameter includes: a key, an encryption parameter, a source address, a destination address, and data length information;

The FSM control module 112 is configured to send the key and encryption parameters to the key stream processing module 12 when a first preset condition is met according to the first parameter sent by the bus from the processing module 111 , sending the source address, destination address and data length information to the bus main processing module 113;

The main bus processing module 113 is configured to read the data to be encrypted according to the source address and data length information sent by the FSM control module 112, and send the data to be encrypted to the encryption processing module 13 ; It is also used to receive the encrypted data sent by the encryption processing module 13 according to the destination address and data length information sent by the FSM control module 112, and output the encrypted data.

In conjunction with the encryption device shown in Figures 1 and 2, specifically, the bus slave processing module 111 is an interface module on the control side, and is used to obtain various parameters required for encryption processing. In this embodiment, the The parameter is the first parameter, which specifically includes: key, encryption parameter, source address, destination address and data length information; wherein, the source address is the buffer address of the data to be encrypted read by the data storage module 11; the The destination address is the cache address of the encrypted data received by the data storage module 11 . Preferably, the interface adopted by the bus slave processing module 111 includes but not limited to an AXI slave interface or an AHB slave interface.

Described FSM control module 112 is the control center of described encryption device; ) to set the timer clock, and when the timer clock of each of the above-mentioned processing modules is turned on, it is determined that the above-mentioned processing modules are in the working mode, that is, the first preset condition is met; at this time, the FSM control module 112 will The key and encryption parameters are sent to the key stream processing module 12, so that the key stream processing module 12 generates a key stream according to the key and the encryption parameters; the source address, destination address and The data length information is sent to the bus main processing module 113, so that the bus main processing module 113 starts to read in the data to be encrypted from the external memory;

Specifically, the bus master processing module 113 includes: a first cache module and a second cache module; wherein,

The first cache module is configured to read in the data to be encrypted according to the source address and data length information sent by the FSM control module 112, and store the data to be encrypted when a second preset condition is met. Send to the encryption processing module 13;

The second cache module is configured to receive the encrypted data sent by the encryption processing module 13 according to the destination address and data length information sent by the FSM control module 112, and output the encrypted data when the third preset condition is satisfied. the encrypted data.

Specifically, the bus main processing module 113 starts to read the data to be encrypted from the external memory, and writes the data to be encrypted into the The first cache module, when the first cache module is not fully written or the data to be encrypted is not all read in, it continuously reads the data to be encrypted from the external memory until the first cache module writes is full or all the data to be encrypted is read in, then in this embodiment, the second preset condition is that when all the data to be encrypted is read in or the first cache module is full, the The data to be encrypted is sent to the encryption processing module 13; the bus main processing module 113 also writes the encrypted data into the second The cache module, when the second cache module is not full or the encrypted data is not all read in, continue to write the encrypted data until the second cache module is full or the encrypted data is all written, Then in this embodiment, the third preset condition is that when all the encrypted data is written or the second cache module is full, the encrypted data is output to the external memory.

Specifically, in this embodiment, the interface adopted by the bus master processing module 113 includes but is not limited to an AXI master interface or an AHB master interface; specifically, the bus master processing module 113 can adopt the AXImaster interface of AMBA3.0, It is convenient for data read and write operations, which greatly improves the speed of data storage.

The key stream processing module 12 is specifically configured to generate a key stream according to the secret key and encryption parameters sent by the FSM control module 112 . Specifically, the process of generating the key stream is divided into two parts: an initialization phase and a key stream generation phase. Fig. 3 is a logical schematic diagram of the initialization process in the key stream generation process in the embodiment of the present invention; Fig. 4 is a logical schematic diagram of the key stream generation process in the embodiment of the present invention; as shown in Fig. 3 and Fig. 4, the key The key stream processing module 12 is composed of three logical levels: the top level is a 16-level linear feedback shift register (LFSR) 31 , the middle level is a bit reorganization (BR) 32 , and the bottom level is a nonlinear function (F) level 33 . Wherein, the LFSR31 is composed of 16 31-bit registers such as S ₀ to S ₁₅ ; the BR32 extracts 128 bits from the registers of the LFSR31 to form four 32-bit (bit) words (X ₀ , X ₁ , X ₂ and X ₃ ), the first three 32-bit words X ₀ to X ₂ are used for the F layer 33, and the last word X ₃ is used to generate the key stream; wherein, the F layer 33 consists of two 32-bit registers R ₁ and R ₂ , the output is a 32-bit word W.

The process of generating the key stream is divided into two parts, at first is the initialization stage, as shown in Figure 3, utilizes the described key (KEY) that described FSM control module 112 sends, described encryption parameter and constant string D to pass through certain Transform and write to the registers S ₀ ~ S ₁₅ of the LFSR, wherein the encryption parameters include: COUNT, BEARER, DIRECTION; the registers R ₁ and R ₂ are initialized to 0, and the output W of the F layer 33 is shifted feedback to the LFSR31. The following process is repeated 32 times: reorganize the high bit (bit 30-15) of register S ₁₅ and the low bit (bit 15-0) of register S ₁₄ into X ₀ , combine the low bit of register S ₁₁ and the low bit of register S ₉ The high bits are reorganized into X ₁ , the low bits of register S ₇ and the high bits of register S ₅ are reorganized into X ₂ , the low bits of register S ₂ and the high bits of register S ₀ are reorganized into X ₃ ; the F layer 33 pair comes from the BR32 Modulo 32 addition of X ₁ and register R ₁ is assigned to W ₁ , X ₂ from the BR32 and register R ₂ is XORed and assigned to W ₂ ; the low bits of W ₁ and the high bits of W ₂ are recombined first After the linear transformation of L ₁ , carry out S-box transformation and assign it to register R ₁ , after reorganizing the low bits of W ₂ and the high bits of W ₁ , first perform L ₂ linear transformation and then perform S-box transformation and assign it to register R ₂ ; put X ₀ and R ₁ Exclusive OR and then perform modulo 32 addition with R ₂ and assign it to W, shift W to the right by 1 bit and send it to the LFSR31 to register S ₀ , shift register S ₀ to the left by 8 bits, and register S ₄ to the left by 20 bit, shift register S ₁₀ to the left by 21 bits, register S ₁₃ to the left by 17 bits, register S ₁₅ to the left by 15 bits and add the modulus (2 ³¹ -1) to register S ₁₆ , and register S to ₁₆ is assigned to register S ₁₅ , register S ₁₅ is assigned to register S ₁₄ , and so on, until register S ₁ is assigned to register S ₀ , and a cycle is completed.

After the initialization phase is complete, keystream generation begins. As shown in Figure 4. Reorganize the high bits (30~15 bits) of register S ₁₅ and the low bits (15~0 bits) of register S ₁₄ into X ₀ , reorganize the low bits of register S ₁₁ and the high bits of register S ₉ into X ₁ , and reorganize register S ₇ The low bits of register S ₅ and the high bits of register S 5 are recombined into X ₂ , and the low bits of register S ₂ and the high bits of register S ₀ are reorganized into X ₃ ; the F layer 33 modulo 32 the X ₁ from the BR32 and the register R ₁ Add and assign to W ₁ , XOR the X ₂ and register R ₂ from the BR32 and assign to W ₂ ; after recombining the low bits of W ₁ and the high bits of W ₂ , first perform L ₁ linear transformation and then perform S box transformation assignment For register R ₁ , after reorganizing the low bits of W ₂ and the high bits of W ₁ , first perform L ₂ linear transformation and then perform S-box transformation and assign it to register R ₂ ; X ₀ is XORed with register R ₁ and then performed with register R ₂ Modulo 32 is added to W, and this value is discarded; at the same time, register S ₀ is rotated to the left by 8 bits, register S ₄ is rotated to the left by 20 bits, register S ₁₀ is rotated to the left by 21 bits, and register S ₁₃ is rotated to the left by 17 bit, assign register S ₁₅ to register S ₁₆ after circularly shifting 15 bits to the left and add modulus (2 ³¹ -1), assign register S ₁₆ to register S ₁₅ , assign register S ₁₅ to register S ₁₄ , and so on , until register S ₁ is assigned to register S ₀ . Repeat the following steps to continuously generate the key stream: recombine the high bits (30-15 bits) of register S ₁₅ and the low bits (15-0 bits) of register S ₁₄ into X ₀ , combine the low bits of register S ₁₁ and register S ₉ The high bits of register S 7 and the high bits of register S 5 are reorganized into X ₁ , the low bits of register S ₇ and the high bits of register S ₅ are reorganized into X ₂ , and the low bits of register S ₂ and the high bits of register S ₀ are reorganized into X ₃ ; the F layer 33 pair comes from the X ₁ of BR32 and register R ₁ are modulo-32 added and assigned to W ₁ , and X ₂ from the BR32 and register R ₂ are XORed and assigned to W ₂ ; after recombining the low bits of W ₁ and the high bits of W ₂ After performing L1 linear transformation, perform S _- box transformation and assign it to register R1, recombine the low bits _of W2 and the high bits _of W1, then perform L2 linear transformation and then perform S _- box transformation and assign it to register _{R2 ;} combine _X0 with register After XOR of R ₁ , add modulo 32 with register R ₂ and assign it to W, and XOR W with X ₃ to generate the key stream; at the same time, register S ₀ is rotated to the left by 8 bits, and register S ₄ is rotated to the left by 20 bits , the register S ₁₀ is rotated to the left by 21 bits, the register S ₁₃ is rotated to the left by 17 bits, the register S ₁₅ is rotated to the left by 15 bits and the modulus (2 ³¹ -1) is added to the register S ₁₆ , and the register S ₁₆ assign to register S ₁₅ , assign register S ₁₅ to register S ₁₄ , and so on until register S ₁ is assigned to register S ₀ .

In the embodiment of the present invention, the key stream processing module 12 is configured to generate multiple key streams in parallel according to the key and encryption parameters.

The generation of the key stream in the embodiment of the present invention will be further described in detail below with specific examples.

The initialization phase is performed first. Specifically, the initial values of the 16 registers S0-S15 of the LFSR are preset, and the initial values of the 16 registers are preset as the following 16 character strings, as follows:

Let D be the constant string of 240bit, be made up of 16 character substrings of 15bit, comprise: d0, d1 to d15; The 16 substrings of setting in the present embodiment are only a preferred embodiment, in specific practical application, can Set up according to the actual situation;

Then D=d0||d1||...||d15;

in,

d0=1000100110101112;

d1=0100110101111002;

d2=1100010011010112;

d3=0010011010111102;

d4=1010111100010012;

d5=0110101111000102;

d6=1110001001101012;

d7=0001001101011112;

d8=1001101011110002;

d9=0101111000100112;

d10=1101011110001002;

d11=0011010111100012;

d12=1011110001001102;

d13=0111100010011012;

d14=1111000100110102;

d15=1000111101011002.

When 0≤i≤15, S _i =k _i ||di||iv _i ; wherein, _ki and iv _i are intermediate parameters, and the unit is byte.

Among them, IV[0]=COUNT[0];

IV[1]=COUNT[1];

IV[2]=COUNT[2];

IV[3]=COUNT[3];

IV[4]=BEARER||000 ₂ ;

IV[5]=IV[6]=IV[7]=000000002 _;

IV[8]=IV[0]⊕(DIRECTION<<7);

IV[9]=IV[1];

IV[10]=IV[2];

IV[11]=IV[3];

IV[12]=IV[4];

IV[13]=IV[5];

IV[14]=(DIRECTION<<7);

IV[15]=IV[7];

Among them, || means splicing, ⊕ means bitwise XOR, Indicates modulo 32 addition, S _iH is the high bit of register i, specifically 30~15 bits of register i; S _iL is the low bit of register i, specifically 15~0 bits of register i, (a1, a2,...,an) →(b1,b2,…,bn) indicates that the assignment from a to b is parallel; 000 ₂ and 00000000 ₂ respectively indicate the binary value 0; COUNT, BEARER and DIRECTION respectively indicate encryption parameters.

Further, register R ₁ and register R ₂ are assigned an initial value of 0 respectively.

The following process is repeated 32 times:

First extract the register bits in the LFSR and reorganize them into word X ₀ ~ word X ₃ :

Specifically, X ₀ =S _15H ||S _14L ;

X ₁ =S _11L ||S _9H ;

X ₂ =S _7L ||S _5H ;

X ₃ =S _2L ||S _0H ;

Among them, S _15H represents the high bit of register S ₁₅ ; S _14L represents the low position of register S ₁₄ ; S _11L represents the low position of register S ₁₁ ; S _9H represents the high position of register S ₉ ; S _7L represents the low position of register S ₇ ; S _5H represents _The high bit of the register S5 _{; S2L} means the low bit of the register S2; _S0H means the high bit of the register _S0 ; wherein, the above-mentioned high bits are the 30th to 15th bits, and the above-mentioned low bits are the 15th to 0th bits.

Further, X ₀ ~ X ₃ are respectively sent to F for processing, specifically including:

W ₂ =R ₂ ⊕X ₂ ;

R ₁ =S(L ₁ (W _1L ||W _2H ));

R ₂ ＝S(L ₂ (W _2L ||W _1H )).

Among them, S represents the S-box transformation, and the S-box transformation is to transform the 32-bit input into a 32-bit output through the lookup table S ₀ or S ₁ ; L ₁ and L ₂ represent a linear transformation respectively, which is to transform the 32-bit The input linearly transforms into a 32-bit output, specifically:

L ₁ (X)＝X⊕(X<<< ₃₂ 2)⊕(X<<< ₃₂ 10)⊕(X<<< ₃₂ 18)⊕(X<<< ₃₂ 24);

L ₂ (X)＝X⊕(X<<< ₃₂ 8)⊕(X<<< ₃₂ 14)⊕(X<<< ₃₂ 22)⊕(X<<< ₃₂ 30).

Finally, the W generated by F is sent to the LFSR initialization stage to update the register:

v＝2 ¹⁵ S ₁₅ +2 ¹⁷ S ₁₃ +2 ²¹ S ₁₀ +2 ²⁰ S ₄ +(1+2 ⁸ )S ₀ mod(2 ³¹ -1);

S ₁₆ =(v+u)mod(2 ³¹ -1);

Among them, v and u are intermediate parameters; mod is a modulo function.

When S ₁₆ =0, then S16=2 ³¹ -1;

(S ₁ , S ₂ , . . . , S ₁₅ , S ₁₆ ) → (S ₀ , S ₁ , . . . , S ₁₄ , S ₁₅ ).

After the initialization is completed, the encryption device starts to generate the key stream. The process is as follows:

First, extract the register bits in the LFSR and reorganize them into X ₀ ~ X ₃ as:

X ₀ ＝S _15H ||S _14L ;

X ₁ =S _11L ||S _9H ;

X ₂ =S _7L ||S _5H ;

X ₃ =S _2L ||S _0H ;

Among them, S _15H represents the high bit of register S ₁₅ ; S _14L represents the low position of register S ₁₄ ; S _11L represents the low position of register S ₁₁ ; S _9H represents the high position of register S ₉ ; S _7L represents the low position of register S ₇ ; S _5H represents _The high bit of the register S5 _{; S2L} means the low bit of the register S2; _S0H means the high bit of the register _S0 ; wherein, the above-mentioned high bits are the 30th to 15th bits, and the above-mentioned low bits are the 15th to 0th bits.

In the second step, X ₀ ~ X ₃ are sent to F for processing. Except for discarding W in the first run and directly entering the fourth step, the remaining W is retained in each run and sent to the third step, specifically including:

W ₂ =R ₂ ⊕X ₂ ;

R ₁ =S(L ₁ (W _1L ||W _2H ));

R ₂ =S(L ₂ (W _2L ||W _1H ).

Wherein, S represents the S-box transformation, and the S-box transformation is to transform the 32-bit input into a 32-bit output through the lookup table S ₀ or S ₁ ; L ₁ and L ₂ represent a linear transformation respectively, and the 32-bit The input is linearly transformed into a 32-bit output, specifically:

L ₁ (X)＝X⊕(X<<< ₃₂ 2)⊕(X<<< ₃₂ 10)⊕(X<<< ₃₂ 18)⊕(X<<< ₃₂ 24);

L ₂ (X)＝X⊕(X<<< ₃₂ 8)⊕(X<<< ₃₂ 14)⊕(X<<< ₃₂ 22)⊕(X<<< ₃₂ 30).

The third step, LFSR key stream generation, specifically includes:

Z=W⊕X3;

The fourth step is to update the register during the LRSR key stream generation process, including:

S ₁₆ ＝2 ¹⁵ S ₁₅ +2 ¹⁷ S ₁₃ +2 ²¹ S ₁₀ +2 ²⁰ S ₄ +(1+2 ⁸ )S ₀ mod(2 ³¹ -1);

If S ₁₆ =0, then S ₁₆ =2 ³¹ -1;

(S ₁ , S ₂ , . . . , S ₁₅ , S ₁₆ ) → (S ₀ , S ₁ , . . . , S ₁₄ , S ₁₅ ).

Repeat the above steps to generate a 32-bit key stream after each repetition.

Wherein, the encryption processing module 13 requires the key stream processing module 12 to generate L=┌LENGTH/32┐+2 32-bit key streams, wherein, ┌┐ means rounding up. The generated key stream can be represented by _zi , and in this embodiment, the _zi can be z[0], z[1], ..., z[32L-1]; wherein, the z[0] is The most significant of the first 32bit keystream, z[31] is the least significant of the first 32bit keystream. For i=0, 1, 2,..., 32L-1, set z _i =z[i]||z[i+1]||...||z[i+31], each z _i is 32bit .

Specifically, the encryption processing module 13 processes the data to be encrypted and the key stream according to a first encryption method to obtain encrypted data; wherein, the first encryption method is an integrity algorithm; Processing the data to be encrypted and the key stream according to the integrity algorithm is a prior art process, which will not be repeated here.

Further, after the encryption processing module 13 processes the data through the integrity algorithm, it needs to add a check code (MAC) at the end of the data, and use the data carrying the MAC as encrypted data.

Specifically, the process of determining the MAC includes:

Let T be 32 bits 0, and the value range of i is i=0, 1, 2, ..., LENGTH-1, LENGTH, 32(L-1);

When i=0, if a certain bit in M[i+n-1], ..., M[i+1], M[i] is 1, then the corresponding z _i+n-1 , ..., Set valid values for z _i+1 and z _i (you can set z _i =z[i]||z[i+1]||...||z[i+31], each z _i is 32bit); Otherwise, the corresponding z _i+n-1 ,..., z _i+1 , z _i are set to 0, and substituting T=T⊕z _i+n-1 ⊕...⊕z _i+1 ⊕z _i to get T in i = 0, the result of a parallel calculation;

When i=1, if a certain bit of M[i+2n-1], ..., M[i+n+1], M[i+n] is 1, then the corresponding z _i+2n-1 , ..., z _i+n+1 , z _i+n take valid values (zi _i =z[i]||z[i+1]||...||z[i+31] can be set, each z _i are all 32bit); otherwise the corresponding z _i+2n-1 , ..., z _i+n+1 , z _i+n take 0, and substitute T=T⊕z _i+2n-1 ⊕…⊕z _{i +n+1} ⊕z _i+n to get the result of a parallel calculation of T when i=1;

and so on. When i=LENGTH, regardless of the value of M[i], T=T⊕z _LENGTH . Finally when i=32(L-1), MAC=T⊕z _32(L-1) ;

Wherein, _zi represents the key stream generated by the key stream processing module 12; M[i] represents the data to be encrypted by the encryption processing module 13, wherein, i represents a bit, for example, M[0] represents data Bit 0 of ; T is an intermediate variable whose initial value is 0.

In this embodiment, the encryption device can be applied in each node network element of data transmission, such as an evolved node (eNB), etc., and the data storage module 11 in the encryption device can be implemented by an interface and a memory in practical applications ; The key stream processing module 12 in the encryption device can be used in practical applications by a central processing unit (CPU, Central Processing Unit), a digital signal processor (DSP, Digital Signal Processor) or a programmable gate array (FPGA) in the encryption device. , Field-ProgrammableGateArray) combined with registers; the encryption processing module 13 in the encryption device can be implemented by CPU, DSP or FPGA in practical applications.

Based on the encryption device described above, an embodiment of the present invention also provides an encryption method; FIG. 5 is a schematic flow diagram of the encryption method in an embodiment of the present invention; as shown in FIG. 5 , the method includes:

Step 501: Obtain a first parameter; the first parameter includes: a key, an encryption parameter, a source address, a destination address, and a data length.

Here, the acquiring the first parameter includes: acquiring the first parameter by using an AXI master interface or an AHB master interface including but not limited to.

Step 502: Generate a key stream according to the key and encryption parameters in the first parameter.

Here, the generating a key stream according to the key and encryption parameters in the first parameter includes: generating multiple key streams in parallel according to the key and encryption parameters in the first parameter.

Step 503: Read in the data to be encrypted, process the data to be encrypted and the key stream according to the first encryption method to obtain encrypted data, and output the encrypted data.

Here, the reading of the data to be encrypted includes: reading the data to be encrypted by using an AXI master interface or an AHB master interface including but not limited to;

Correspondingly, said outputting said encrypted data includes: adopting but not limited to AXI main interface or AHB main interface to output said encrypted data; specifically, said AXI main interface can adopt AMBA3.0 AXImaster interface, convenient Data read and write operations greatly improve the speed of data storage.

Those skilled in the art should understand that the encryption method in the embodiment of the present invention can be understood with reference to the relevant description of the foregoing encryption device.

Those skilled in the art should understand that the embodiments of the present invention may be provided as methods, apparatuses, or computer program products. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, optical storage, etc.) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus, and computer program products according to embodiments of the invention. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.

Claims (10)

1. An encryption device, characterized in that the encryption device comprises: a data storage module, a key stream processing module and an encryption processing module; wherein, The data storage module is configured to obtain a first parameter, and when a first preset condition is met, send the key and encryption parameters in the first parameter to the key stream processing module; the first parameter Including: key, encryption parameter, source address, destination address and data length; it is also used to read in the data to be encrypted according to the source address and data length in the first parameter, and send the data to be encrypted to the The encryption processing module; also used for receiving the encrypted data sent by the encryption processing module according to the destination address and data length in the first parameter, and outputting the encrypted data; The key stream processing module is configured to receive the key and encryption parameters in the first parameter sent by the data storage module, generate a key stream according to the key and encryption parameters, and convert the key stream to sent to the encryption processing module; The encryption processing module is configured to receive the data to be encrypted sent by the data storage module and the key stream sent by the key stream processing module, and convert the data to be encrypted and the key The stream is processed according to the first encryption method to obtain encrypted data, and the encrypted data is sent to the data storage module. 2. The device according to claim 1, wherein the data storage module comprises: a bus slave processing module, a finite state machine (FSM) control module, and a bus master processing module; wherein, The bus slave processing module is used to obtain a first parameter, and send the first parameter to the FSM control module; the first parameter includes: key, encryption parameter, source address, destination address and data length information ; The FSM control module is configured to send the key and encryption parameters to the key stream processing module when the first preset condition is met according to the first parameter sent by the bus from the processing module, and send the Send the source address, destination address and data length information to the main bus processing module; The main bus processing module is used to read the data to be encrypted according to the source address and data length information sent by the FSM control module, and send the data to be encrypted to the encryption processing module; Receive the encrypted data sent by the encryption processing module according to the destination address and data length information sent by the FSM control module, and output the encrypted data. 3. The device according to claim 2, wherein the bus master processing module comprises: a first cache module and a second cache module; wherein, The first cache module is configured to read in the data to be encrypted according to the source address and data length information sent by the FSM control module, and send the data to be encrypted when a second preset condition is met to the encryption processing module; The second cache module is configured to receive the encrypted data sent by the encryption processing module according to the destination address and data length information sent by the FSM control module, and output the encrypted data when a third preset condition is met. data. 4. The device according to claim 2, wherein the interface adopted by the bus master processing module includes but is not limited to an AXI master interface or an AHB master interface. 5. The device according to claim 2, wherein the interface adopted by the bus slave processing module includes but not limited to an AXI slave interface or an AHB slave interface. 6. The device according to claim 1, wherein the key stream processing module is configured to generate multiple key streams in parallel according to the key and encryption parameters. 7. An encryption method, characterized in that the method comprises: Obtain a first parameter; the first parameter includes: a key, an encryption parameter, a source address, a destination address, and a data length; generating a key stream according to the key and encryption parameters in the first parameter; Reading in the data to be encrypted, processing the data to be encrypted and the key stream according to a first encryption method to obtain encrypted data, and outputting the encrypted data. 8. The method according to claim 7, wherein said generating a key stream according to the key and encryption parameters in the first parameter comprises: according to the key and encryption parameters in the first parameter Generate multiple keystreams in parallel. 9. The method according to claim 7, wherein said obtaining the first parameter comprises: obtaining the first parameter by using an AXI master interface or an AHB master interface including but not limited to. 10. The method according to claim 7, wherein said reading in the data to be encrypted comprises: reading in the data to be encrypted by using an AXI master interface or an AHB master interface including but not limited to; Correspondingly, the outputting the encrypted data includes: outputting the encrypted data by using an AXI master interface or an AHB master interface including but not limited to.