CN105070661B

CN105070661B - A kind of preparation method and structure of power unit structure

Info

Publication number: CN105070661B
Application number: CN201510509369.XA
Authority: CN
Inventors: 夏超; 张琦
Original assignee: East Branch China Electronic Product Reliability And Environmental Testing Research Institute mll
Current assignee: East Branch China Electronic Product Reliability And Environmental Testing Research Institute mll
Priority date: 2015-08-19
Filing date: 2015-08-19
Publication date: 2019-02-01
Anticipated expiration: 2035-08-19
Also published as: CN105070661A

Abstract

The embodiment of the invention discloses a kind of preparation methods of power unit structure to carry out high annealing, activation injection ion, highly doped n-type drift region is from device surface to buried oxide layer upper surface by carrying out phosphorus injection on thin film SOI disk；Silicon etching is carried out, until buried oxide layer, forms SiO₂Dielectric layer window carries out SiO₂Deposition carries out SiO₂Etching carries out polysilicon deposition until buried oxide layer surface, forms polysilicon window；Phosphorus injection is carried out by the photolithography plate of specific customization, then carries out prolonged high annealing；It forms drain electrode, source electrode, grid and grid oxygen and polysilicon gate, polysilicon gate is connected with the grid in drift region；Deposit field oxygen SiO₂And metal, and metal is performed etching, source, leakage, grid metal are formed, so as to effectively improve device electric breakdown strength, reduces device on-resistance.

Description

A kind of preparation method and structure of power unit structure

Technical field

The present embodiments relate to the technical field of semiconductor devices more particularly to a kind of preparation sides of power unit structure Method and structure.

Background technique

Power integrated circuit is sometimes referred to as high voltage integrated circuit, is the important branch of modern electronics, can be various power Transformation and energy processing unit provide high speed, high integration, the new-type circuit of low-power consumption and Flouride-resistani acid phesphatase, are widely used in electric power control The current consumptions fields and national defence, space flight etc. such as system, automotive electronics, display device driving, communication and illumination processed are all more important Field.Its application range expands rapidly, and to the high tension apparatus of its core, higher requirements are also raised.

For power device MOSFET, first, under the premise of guaranteeing breakdown voltage, it is necessary to reduction device as much as possible Conducting resistance improve device performance.But institute is formed there are a kind of approximate quadratic relationship between breakdown voltage and conducting resistance " the silicon limit " of meaning.Second, it is necessary to it is integrated convenient for high-low pressure, in smart-power IC, in addition to Power processing circuit, further include Control circuit, logic circuit protect circuit, the low-voltage circuits such as interface circuit, therefore power device cannot influence low-voltage circuit Operation, must have a good isolation between the two, SOI technology due to its Fully dielectric isolation, the advantage that speed is fast, low in energy consumption, The most market share is occupied in the application of middle low power rapidly.When device pressure resistance is in middle a small range, indulge Influence to pressure resistance is relatively small, and lateral pressure resistance determines the breakdown voltage of device.The electricity of traditional lateral LDMOS device structure Peak value be generally focused on the source electrode and drain electrode both ends of device, the entire U-shaped distribution of drift region electric field, and surface field compared with It is high.Traditional lateral RESURF SOI technology, such as field plate techniques, thin silicon membrane technology etc. improve drift to a certain extent Electric field in the middle part of area, but device performance improves limited, and makes device surface electric field higher, increase in device use process can By property problem.

Summary of the invention

The purpose of the embodiment of the present invention is to propose the preparation method and structure of a kind of power unit structure, it is intended to how to have Electric field and the problem of improve internal electric field in the middle part of the raising drift region of effect.

For this purpose, the embodiment of the present invention uses following technical scheme:

A kind of preparation method of power unit structure, the preparation method include:

Phosphorus injection is carried out on thin film SOI disk, carries out high annealing, activation injection ion carries out silicon etching, until Buried oxide layer forms SiO₂Dielectric layer window carries out SiO₂Deposition carries out SiO₂Etching, until buried oxide layer surface, forms polycrystalline Silicon window carries out polysilicon deposition；

Phosphorus injection is carried out by the photolithography plate of specific customization, then carries out prolonged high annealing；

It forms drain electrode, source electrode, grid and grid oxygen and polysilicon gate, polysilicon gate is connected with the grid in drift region；

Deposit field oxygen SiO₂And metal, and metal is performed etching, form source, leakage, grid metal.

Preferably, the high annealing, activation injection ion annealing temperature be 800~900 DEG C, annealing time be 2~ 5min forms highly doped n-type drift region.

Preferably, the SiO of the formation₂The two edges of dielectric layer window apart from highly doped n-type drift region two edges 0.5~ 1μm。

Preferably, polysilicon window two edges are apart from 0.5~1 μm of media slot two edges.

Preferably, the photolithography plate by specific customization carries out the annealing that phosphorus injection carries out prolonged high annealing again Temperature is 900~1200 DEG C, and the time is 400~800min, so that the doping concentration of polysilicon is linearly increasing from source to leaking.

Preferably, the doping concentration inside the polysilicon gradually increases from one end close to source electrode to close to one end of drain electrode Add, approximately linear distribution, and in SiO₂Slot two sides form the n-layer of high-dopant concentration, and highly doped n-type drift region is from device Surface to buried oxide layer upper surface.

A kind of power unit structure, the power unit structure include:

P type substrate, buried oxide layer, source electrode, grid, N-shaped deviate area, linear doping polysilicon layer, highly doped n-type floor, SiO₂ And drain electrode；

For the P type substrate in the bottom of the power device, the buried oxide layer is described on the P type substrate, described Doping concentration inside linear doping polysilicon is gradually increased from one end close to the source electrode to one end close to the drain electrode, Linear distribution, and in SiO₂The n-layer of slot two sides formation high-dopant concentration.

Preferably, the SiO of the formation₂The two edges of dielectric layer window apart from highly doped n-type drift region two edges 0.5~ 1μm；Polysilicon window two edges are apart from 0.5~1 μm of media slot two edges.

The embodiment of the present invention provides a kind of preparation method of power unit structure, by carrying out phosphorus on thin film SOI disk Injection carries out high annealing, and activation injection ion carries out silicon etching, until buried oxide layer, forms SiO₂Dielectric layer window, into Row SiO₂Deposition carries out SiO₂Etching carries out polysilicon deposition until buried oxide layer surface, forms polysilicon window；Pass through spy The photolithography plate very customized carries out phosphorus injection, then carries out prolonged high annealing；Formed drain electrode, source electrode, grid and grid oxygen and Grid in polysilicon gate, polysilicon gate and drift region are connected；Deposit field oxygen SiO₂And metal, and metal is performed etching, it is formed Source, leakage, grid metal reduce device on-resistance so as to effectively improve device electric breakdown strength.

Detailed description of the invention

Fig. 1 is the flow diagram of the preparation method of power unit structure of the embodiment of the present invention；

Fig. 2 is a kind of structural schematic diagram of photolithography plate provided in an embodiment of the present invention；

Fig. 3 is a kind of schematic diagram of phosphorus injection provided in an embodiment of the present invention；

Fig. 4 is a kind of schematic diagram for forming highly doped n-type offset area provided in an embodiment of the present invention；

Fig. 5 is a kind of formation SiO provided in an embodiment of the present invention₂The schematic diagram of dielectric layer window；

Fig. 6 is a kind of SiO provided in an embodiment of the present invention₂The schematic diagram of deposition；

Fig. 7 is a kind of schematic diagram for forming polysilicon window provided in an embodiment of the present invention；

Fig. 8 is a kind of polysilicon deposition provided in an embodiment of the present invention and the schematic diagram for carrying out phosphorus injection；

Fig. 9 is a kind of schematic diagram for forming source electrode, drain electrode, grid provided in an embodiment of the present invention；

Figure 10 is a kind of schematic diagram for forming metal electrode provided in an embodiment of the present invention；

10 be drain electrode, and 11 be SiO₂, 12 attach most importance to doped n-type layer, and 13 be linear doping polysilicon layer, and 14 deviate area for N-shaped, 15 be grid, and 16 be source electrode, and 17 be buried oxide layer, and 18 be P type substrate.

Specific embodiment

The embodiment of the present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this Locate described specific embodiment and is used only for explaining the embodiment of the present invention, rather than the restriction to the embodiment of the present invention.In addition also It should be noted that only parts related to embodiments of the present invention are shown rather than entire infrastructure for ease of description, in attached drawing.

Embodiment one

It is the flow diagram of the preparation method of power unit structure of the embodiment of the present invention with reference to Fig. 1, Fig. 1.

In example 1, the preparation method of the power unit structure includes:

Step 101, phosphorus injection is carried out on thin film SOI disk, carries out high annealing, and activation injection ion carries out silicon quarter Erosion, until buried oxide layer, forms SiO₂Dielectric layer window carries out SiO₂Deposition carries out SiO₂Etching, until buried oxide layer surface, Polysilicon window is formed, polysilicon deposition is carried out；

Step 102, phosphorus injection is carried out by the photolithography plate of specific customization, then carries out prolonged high annealing；

Specifically, photolithography plate is refering to what is shown in Fig. 2, Fig. 2 is a kind of structural representation of photolithography plate provided in an embodiment of the present invention Figure.

Step 103, drain electrode, source electrode, grid and grid oxygen and polysilicon gate, the grid phase in polysilicon gate and drift region are formed Even；

Step 104, field oxygen SiO is deposited₂And metal, and metal is performed etching, form source, leakage, grid metal.

Specifically, specific step is as follows for process flow:

(1) phosphorus injection is carried out on thin film SOI disk；(Fig. 3, Fig. 3 are a kind of phosphorus injections provided in an embodiment of the present invention Schematic diagram)

(2) high annealing is carried out, activation injection ion forms highly doped n-type drift region, and annealing temperature is 800~900 DEG C, annealing time is 2~5min；(Fig. 4, Fig. 4 are that a kind of highly doped n-type that formed provided in an embodiment of the present invention deviates showing for area It is intended to)

(3) silicon etching is carried out, until buried oxide layer, forms SiO₂Dielectric layer window, window two edges are apart from highly doped n-type 0.5~1 μm of drift region two edges；(Fig. 5, Fig. 5 are a kind of formation SiO provided in an embodiment of the present invention₂The signal of dielectric layer window Figure)

(4) SiO is carried out₂Deposition；(Fig. 6, Fig. 6 are a kind of SiO provided in an embodiment of the present invention₂The schematic diagram of deposition)

(5) SiO is carried out₂Etching, until buried oxide layer surface, forms polysilicon window, window two edges are apart from media slot 0.5~1 μm of two edges；(Fig. 7, Fig. 7 are a kind of schematic diagrames for forming polysilicon window provided in an embodiment of the present invention)

(6) polysilicon deposition is carried out；(schematic diagram that Fig. 8, Fig. 8 are a kind of polysilicon deposition provided in an embodiment of the present invention)

(7) phosphorus injection (photolithography plate is shown in figure (2)) is carried out by the photolithography plate of specific customization, then carries out prolonged high temperature Annealing, make the doping concentration of polysilicon from source to leak it is linearly increasing, annealing temperature be 900~1200 DEG C, the time be 400~ 800min；(schematic diagram that Fig. 9, Fig. 9 are a kind of phosphorus injection provided in an embodiment of the present invention)

(8) drain electrode, source electrode, grid and grid oxygen are formed and polysilicon gate, polysilicon gate is connected with the grid in drift region, had Body technology is identical as traditional handicraft；(schematic diagram that Figure 10 is a kind of power unit structure provided in an embodiment of the present invention)

Specifically, traditional SOI LDMOS device structure middle low power should occasion under, it is most of all to pass through It elongates drift region length or reduces drift doping concentration to meet the needs of breakdown voltage, and both modes can all cause Device on-resistance increases, and limits further increasing for device performance, also becomes SOI power device and move towards large-scale application Bottleneck.The invention proposes a kind of longitudinal direction RESURF structure of SOI power device, such as Figure 10, traditional lateral RESURF technologies It is all located at device surface, and longitudinal direction RESURF technology is in inside device drift region, in the structure, is in SiO₂Polycrystalline in slot Prolonged high annealing is carried out again after the photolithography plate injection that silicon layer passes through specific customization, can make the doping inside polysilicon Concentration is gradually increased from one end close to source electrode to close to one end of drain electrode, approximately linear distribution, while in SiO₂Slot two sides The n-layer of high-dopant concentration is formed, other structures are then identical as traditional SOI LDMOS structure.Since polysilicon doping concentration is close Like linear distribution and depth directes reach buried oxide layer, therefore, forms longitudinal RESURF technology, the polysilicon layer of linear doping can be adjusted Drift region electric field processed, so that drift region field distribution is more uniform, it can be in SiO after highly doped n-layer is completely depleted₂It stays on surface Lower a large amount of immovable positive charge improves the charge density on dielectric layer both sides in conjunction with the electronics that polysilicon layer introduces, according to The electric field of Gauss theorem, dielectric layer can greatly increase, while also result in effectively increasing for drift region electric field, improve device Breakdown voltage.In break-over of device, the polysilicon layer for connecting grid can attract electronics aggregation on dielectric layer both sides, form an electricity Sub- accumulation layer flows through drift region for electric current and provides the current channel of a low-resistance, causes device on-resistance to greatly reduce, in addition The presence of polysilicon layer also contributes to drift region and exhausts, so that under the conditions of same breakdown voltage, the doping concentration of device drift region It is greatly improved, improves SOI power device performance.

In the present invention, longitudinal RESURF technology is introduced to traditional semiconductor power device LDMOS structure, improves and hits Wear the tradeoff between voltage and conducting resistance.The doping concentration of polysilicon in deep trouth is gradually increased from source to leakage, The distribution of drift region electric fields uniform can be modulated, secondly, a large amount of immovable positive charge is left after the fully- depleted of drift region, so that being situated between The charge density of matter layer surface greatly increases, and effectively raises electric field in the middle part of drift region, different from traditional RESURF technology, On the one hand the high electric field on surface can be introduced drift region bottom by longitudinal RESURF technology, avoid the occurrence of surface field concentration, separately On the one hand the doping concentration of drift region bottom can be made to be greatly improved, improves the breakdown voltage of device.In break-over of device When, the polysilicon layer for connecting grid can make close to SiO₂There is charge accumulated in layer surface, formed the low impedance path of electric current with And increased drift doping concentration can effectively reduce the conducting resistance of device, device performance be improved, especially in The occasion of low-power applications.

Embodiment two

It is the schematic diagram of power unit structure of the embodiment of the present invention with reference to Figure 10, Figure 10.

In example 2, the power unit structure includes:

Invention describes a kind of high-performance semiconductor power unit structures and preparation method thereof of longitudinal direction RESURF technology. The breakdown voltage of lateral power LDMOS structure is codetermined by laterally pressure-resistant and longitudinal pressure resistance, and in a certain range, The laterally pressure-resistant and drift doping concentration directly proportional with drift region length of device is inversely proportional, and the conducting resistance of device is then just It is good on the contrary, therefore, mutually restricted between the breakdown voltage and conducting resistance of lateral power, there are a contradictory relation, In the present invention, longitudinal RESURF technology is introduced to traditional semiconductor power device LDMOS structure, improve breakdown voltage and is led The tradeoff being powered between hindering.The doping concentration of polysilicon in deep trouth is gradually increased from source to leakage, can modulate drift The distribution of area's electric fields uniform is moved, secondly, a large amount of immovable positive charge is left after the fully- depleted of drift region, so that dielectric layer surface Charge density greatly increases, and electric field in the middle part of drift region is effectively raised, different from traditional RESURF technology, longitudinal RESURF On the one hand the high electric field on surface can be introduced drift region bottom by technology, avoid the occurrence of surface field concentration, on the other hand can be with So that the doping concentration of drift region bottom is greatly improved, the breakdown voltage of device is improved.In break-over of device, grid is connected Polysilicon layer can make close to SiO₂There is charge accumulated in layer surface, formed electric current low impedance path and increased drift Area's doping concentration can effectively reduce the conducting resistance of device, device performance be improved, especially in middle low power application Occasion.

Describe the technical principle of the embodiment of the present invention in conjunction with specific embodiments above.These descriptions are intended merely to explain this The principle of inventive embodiments, and it cannot be construed to the limitation to protection scope of the embodiment of the present invention in any way.Based on herein Explanation, those skilled in the art, which does not need to pay for creative labor, can associate the other specific of the embodiment of the present invention Embodiment, these modes are fallen within the protection scope of the embodiment of the present invention.

Claims

1. A preparation method of a power device structure, wherein the preparation method comprises:

Phosphorus implantation on thin film SOI wafers;

performing a first high-temperature annealing treatment to activate the implanted ions to form a heavily doped n-type drift region, the heavily doped n-type drift region extending from the device surface to the upper surface of the buried oxide layer;

Silicon etching is performed in the heavily doped n-type drift region until the buried oxide layer to form a _SiO2 dielectric groove, and the remaining part of the heavily doped n-type drift region forms a heavily doped n-type layer;

Carry out SiO ₂ deposition, and form a SiO ₂ dielectric layer in the SiO ₂ dielectric groove;

Perform SiO ₂ etching until the surface of the buried oxide layer to form a polysilicon groove;

Polysilicon deposition is performed to form a polysilicon layer in the polysilicon groove;

Phosphorus is implanted through a preset lithography plate, and then a second high-temperature annealing treatment is performed. The annealing time is 400-800 minutes to form a linearly doped polysilicon layer. The doping concentration inside the linearly doped polysilicon layer ranges from the end close to the source to the The end close to the drain gradually increases, showing a linear distribution;

forming a drain region, a source region, a gate oxide and a polysilicon gate, and the polysilicon gate is connected to the linearly doped polysilicon layer in the heavily doped n-type drift region;

Field oxygen SiO ₂ and metal are deposited, and the metal is etched to form source metal, drain metal and gate metal.

2 . The preparation method according to claim 1 , wherein the annealing temperature of the first high-temperature annealing treatment is 800˜900° C., and the annealing time is 2˜5 min. 3 .

3 . The preparation method according to claim 1 , wherein the two opposite first edges of the SiO ₂ dielectric trench are respectively 0.5-1 μm away from the two edges corresponding to the heavily doped n-type drift region; 3 . The first edge is parallel to the direction from the source to the drain.

4 . The preparation method according to claim 1 , wherein the two opposite edges of the polysilicon groove are respectively 0.5-1 μm away from the two corresponding edges of the SiO ₂ dielectric groove; The source-to-drain directions are parallel.

5 . The preparation method according to claim 1 , wherein the annealing temperature of the second high-temperature annealing treatment is 900-1200° C. 6 .

6. A power device structure, wherein the power device structure comprises:

P-type substrate, buried oxide layer, source electrode, gate electrode, n-type drift region, linearly doped polysilicon layer, heavily doped n-type layer, _SiO2 dielectric layer and drain electrode;

the P-type substrate is at the bottom of the power device, the buried oxide layer is on the P-type substrate, and the n-type drift region is on the buried oxide layer;

The heavily doped n-type layer is formed by performing phosphorus ion implantation and annealing in the n-type drift region, and the heavily doped n-type layer is from the surface of the n-type drift region to the upper surface of the buried oxide layer;

The SiO ₂ dielectric layer is formed in a SiO _{2 dielectric groove in the heavily doped n-type layer, and the SiO 2} _dielectric groove extends from the surface of the heavily doped n-type layer to the upper surface of the buried oxide layer;

The linearly doped polysilicon layer is formed in a polysilicon groove in the _SiO2 dielectric layer, and the polysilicon groove extends from the surface of the _SiO2 dielectric layer to the upper surface of the buried oxide layer;

The doping concentration inside the linearly doped polysilicon layer gradually increases from an end close to the source electrode to an end close to the drain electrode, and is linearly distributed.

7 . The power device structure according to claim 6 , wherein the two opposite first edges of the SiO ₂ dielectric groove are respectively 0.5-1 μm away from the two corresponding edges of the heavily doped n-type layer; the The first edge is parallel to the direction from the source electrode to the drain electrode; the two second edges opposite to the polysilicon groove are respectively 0.5-1 μm away from the two edges corresponding to the SiO ₂ dielectric groove; the second edge is parallel to the direction from the source electrode The direction to the drain is parallel.