CN105068335A - 一种ffs阵列基板的制造方法 - Google Patents
一种ffs阵列基板的制造方法 Download PDFInfo
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Abstract
本发明提供一种FFS阵列基板的制造方法,包括以下步骤:在玻璃基板上形成栅极与公共电极,所述栅极形成在所述公共电极的一部分上面;在所述栅极与所述公共电极上形成一层栅极绝缘层;在所述栅极绝缘层上沉淀一层透明金属氧化物半导体层并对所述透明金属氧化物半导体层进行一次图案化处理,以形成半导体有源层前体与像素电极前体;对所述半导体有源层前体的没留有光阻层的两端及所述像素电极前体进行离子注入处理以使它们形成透明导体;最后在所述半导体有源层上形成源极与漏极。本发明的制造方法能够减少FFS阵列基板制造所需光罩次数,提高FFS阵列基板的制造效率。
Description
【技术领域】
本发明涉及液晶显示器技术领域,特别涉及一种FFS阵列基板的制造方法。
【背景技术】
边缘场开关(FringeFieldSwitching,简称FFS)技术,是目前的一种液晶显示器技术,是液晶界为解决大尺寸,高清晰桌面显示器和液晶电视应用而开发的一种广视角技术。FFS液晶面板具有响应时间快、光透过率高,宽视角及较低的色偏等优点。
目前,非晶硅(a-Si)和多晶硅(p-Si)是薄膜晶体管(ThinFilmTransistor,TFT)主流的半导体材料,其中非晶硅应用最为广泛,但是非晶硅具有电子迁移率低、光照稳定性差等问题。多晶硅在电子迁移率方面虽然比非晶硅好,但是具有构造复杂、漏电流大,膜质均一性差等问题。总的来说,随着显示技术的飞快发展,人们对TFT的性能提出了越来越高的要求,非晶硅和多晶硅已经不能完全满足这些要求。
另外,像素电极一般由透明的氧化铟锡(IndiumTinOxide,ITO)材料制成,在制作TFT的半导体有源层和像素电极时,需要采用两道光罩(mask)制程,以分别制作TFT的半导体有源层和像素电极,这样做会需要使用更多的光罩,以及更复杂的制作工艺,降低了生产效率。
【发明内容】
本发明的目的在于提供一种FFS阵列基板的制造方法,该制造方法能够减少光罩次数,提高FFS阵列基板的制造效率。
本发明的技术方案如下:
一种FFS阵列基板的制造方法,包括以下步骤:
在玻璃基板上形成栅极与公共电极,所述栅极形成在所述公共电极的一部分上面;
在所述栅极与所述公共电极上形成一层栅极绝缘层;
在所述栅极绝缘层上沉淀一层透明金属氧化物半导体层;
对所述透明金属氧化物半导体层进行一次图案化处理,以形成半导体有源层前体与像素电极前体,并仅使所述半导体有源层前体的中间部分上面有光阻层;
对所述半导体有源层前体的没有所述光阻层的两端及所述像素电极前体进行离子注入处理,以将它们变成透明导体,使所述半导体有源层前体变为半导体有源层,并使所述像素电极前体变为像素电极;以及
在所述半导体有源层上形成源极与漏极。
优选地,所述步骤还包括,在所述源极、漏极、半导体有源层以及像素电极上形成一层钝化层。
优选地,所述栅极与公共电极的制作过程为:在所述玻璃基板上依次沉淀一层ITO层与一层金属层,再对所述ITO层与所述金属层进行一次图案化处理,以形成所述栅极与所述公共电极。
优选地,所述透明金属氧化物半导体的材料为IGZO。
优选地,所述透明金属氧化物半导体的材料为ITZO。
优选地,所述离子注入的方式为:对所述半导体有源层前体两端与所述像素电极前体进行等离子体处理。
优选地,所述离子为H离子或Ar离子。
优选地,所述的在所述半导体有源层上形成源极与漏极之前,还包括步骤:在所述半导体有源层及所述像素电极上形成一层刻蚀阻挡层,并在所述半导体有源层两端及靠近所述半导体有源层的所述像素电极的一端上对应的所述刻蚀阻挡层形成过孔,使所述半导体有源层两端及靠近所述半导体有源层的所述像素电极的一端暴露出来。
优选地,所述栅极绝缘层的制作材料为氧化硅或氧化硅与氮化硅的双层膜。
优选地,所述刻蚀阻挡层的制作材料为氧化硅。
本发明的有益效果:
本发明的一种FFS阵列基板的制造方法,通过一道光罩同时制造栅极和公共电极,通过一道光罩同时制造半导体有源层和像素电极,能够减少光罩次数,降低了制作成本,提高FFS阵列基板的制造效率,并且用金属氧化物半导体替代非晶硅和多晶硅作为薄膜晶体管的半导体材料,会使得半导体有源层的电子迁移率和开口率更高,光照稳定性以及光透过性更好。
【附图说明】
图1为本发明的实施例1的制造方法流程图;
图2为本发明的实施例1的基板上的形成栅极与公共电极的结构示意图;
图3为本发明的实施例1的基板上的形成栅极绝缘层的结构示意图;
图4为本发明的实施例1的基板上的对金属氧化物半导体进行图案化过程中半导体有源层前体和像素电极前体被光阻层覆盖示意图;
图5为本发明的实施例1的基板上的半导体有源层前体中间部分上面覆盖光阻层示意图;
图6为本发明的实施例1的基板上的半导体有源层前体和像素电极前体被离子注入处理后分别形成半导体有源层和像素电极后的示意图;
图7为本发明的实施例1的基板上的在半导体有源层上形成源极和漏极后的示意图;
图8为本发明的实施例1的基板上的在源极、漏极和像素电极上覆盖钝化层后的示意图;
图9为本发明的实施例2的基板上的在半导体有源层和像素电极上覆盖一层刻蚀阻挡层后的示意图;
图10为本发明的实施例2的基板上的在刻蚀阻挡层上形成源极和漏极后的示意图;
图11为本发明的实施例2的基板上的在源极、漏极和刻蚀阻挡层上形成钝化层后的示意图。
【具体实施方式】
以下各实施例的说明是参考附加的图式,用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语,例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。在图中,结构相似的单元是以相同标号表示。
实施例1
如图1所示为本实施例的一种FFS阵列基板的制造方法的流程图,图2至图8为本实施例制作FFS阵列基板的顺序图。
从图1可以看出,本实施例的一种FFS阵列基板的制造方法,包括以下几个步骤:
S101:如图2所示,在玻璃基板1上形成栅极3与公共电极2,所述栅极3形成在所述公共电极2的一部分上面。具体制作过程为:现在玻璃基板1上沉淀一层ITO层,再在该ITO层上沉淀一层金属层,该金属层的材料可以是铜或铝,也可以是其它金属。然后再对所述ITO层与所述金属层进行一次图案化处理,即通过一道光罩工艺,包括光阻涂布、曝光、显影、刻蚀和去光阻等工序,以形成所述栅极3与所述公共电极2。本步骤中,为了只用一道光罩工艺,就形成公共电极2和栅极3,将栅极3设在了ITO层的一部分上,该部分ITO层与公共电极2相隔开。在现有技术中,通常是先在玻璃基板1上形成栅极3,接着在栅极3上形成栅极绝缘层4,然后才在栅极绝缘层4上形成公共电极2,这种制作方法需要两道光罩工艺分别制作才能完成,本步骤相对于现有技术来说,减少了一道光罩工艺制程,降低了制作成本。
S102:如图3所示,为本实施例的基板上的形成栅极绝缘层的结构示意图。本步骤是在所述栅极3与所述公共电极2上形成一层栅极绝缘层4。该栅极绝缘层4的制作材料可以为氧化硅或者氮化硅,本步骤优选为氧化硅或氧化硅与氮化硅的双层膜,也可以是其它合适的材料。该栅极绝缘层4是通过等离子体增强化学气相沉积(PlasmaEnhancedChemicalVaporDeposition,PECVD)方法沉积形成的。
S103:在所述栅极绝缘层4上沉淀一层透明金属氧化物半导体层。该透明金属氧化物半导体的材料为铟镓锌氧化物(IndiumGalliumZincOxide,IGZO)或者铟锡锌氧化物(IndiumTinZincOxide,ITZO),本实施例优选铟镓锌氧化物。
S104:对所述透明金属氧化物半导体层,即对铟镓锌氧化物层进行一次图案化处理,以形成半导体有源层前体5与像素电极前体6,并仅使所述半导体有源层前体5的中间部分上面有光阻层7。其中,所述图案化处理包括光阻涂布、曝光、显影、刻蚀和去光阻层7等工序。本实施例的一个特别之处就是,在去光阻层7的时候,把像素电极前体6上面的光阻层7全部去掉,而对于半导体有源层前体5,则只是去除它上面两端的光阻层7,保留其中间部分上面的光阻层7,半导体有源层前体5中间部分上面的光阻层7作为下一步骤的离子注入处理的保护层。如图4所示,为本实施例的玻璃基板1上的对金属氧化物半导体进行图案化过程中半导体有源层前体5和像素电极前体6被光阻层7覆盖示意图,如图5所示,为本实施例的玻璃基板1上的半导体有源层前体5中间部分上面覆盖光阻层7示意图。
S105:对所述半导体有源层前体5的没有所述光阻层7的两端及所述像素电极前体6进行离子注入处理,以将它们变成透明导体,使所述半导体有源层前体5变为半导体有源层8,并使所述像素电极前体6变为像素电极9。本实施例的离子注入的方式为:对所述半导体有源层前体5两端与所述像素电极前体6进行等离子体处理,在本步骤中,由于半导体有源层前体5中间部分的上面有光阻层7保护,所以在离子注入的过程中,半导体有源层前体5中间部分不会受到离子注入的影响破坏,仍然维持为半导体,而半导体有源层前体5的两端以及像素电极前体6,由于没有了光阻层7的保护,全部变为导体。另外本实施例优选所述离子为H离子或Ar离子。如图6所示,为本实施例的玻璃基板1上的半导体有源层前体5和像素电极前体6被离子注入处理后分别形成半导体有源层8和像素电极9后的示意图。
从S104和S105这两个步骤可以看出,本实施例在制作半导体有源层8和像素电极9时,只需要一道光罩工艺制程。另外由于本实施例使用金属氧化物半导体即铟镓锌氧化物替代传统的非晶硅或多晶硅,作为TFT半导体有源层8的材料,会使得半导体有源层8的电子迁移率和开口率更高,光照稳定性以及光透过性更好。而在现有技术中,像素电极9一般由ITO制程,半导体有源层8和像素电极9需要两道独立的光罩工艺制程来完成,而且效果没有本实施例好。
S106:在所述半导体有源层8上形成源极10与漏极11。如图7所示,为本实施例的玻璃基板1上的在半导体有源层8上形成源极10和漏极11后的示意图。
除了以上制作步骤外,本实施例还包括,在所述源极10、漏极11、半导体有源层8以及像素电极9上形成一层钝化层12。如图8所示,为本发明的实施例1的玻璃基板1上的在源极10、漏极11和像素电极9上覆盖钝化层12后的示意图。
实施例2
本实施例的前面部分与实施例1的S101~S105相同,所不同的是在S105之后,在所述半导体有源层8上形成源极10与漏极11之前,还包括步骤:在所述半导体有源层8及所述像素电极9上形成一层刻蚀阻挡层13,本实施例优选所述刻蚀阻挡层13的制作材料为氧化硅。另外还在所述半导体有源层8两端,以及靠近所述半导体有源层8的所述像素电极9的一端上对应的所述刻蚀阻挡层13形成过孔,使所述半导体有源层8两端及靠近所述半导体有源层8的所述像素电极9的一端暴露出来,为下一步骤形成源极10和漏极11做准备。
接下来就是在所述半导体有源层8对应的刻蚀阻挡层13上形成源极10和漏极11。在上一步骤中,已经在半导体有源层8和像素电极9上覆盖了一层刻蚀阻挡层13,因此在形成源极10和漏极11的过程中不会损伤到半导体有源层8的中间部分。最后再在源极10、漏极11和刻蚀阻挡层13上面覆盖一层钝化层12,至此所有制作工艺全部完成。
综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。
Claims (10)
1.一种FFS阵列基板的制造方法,其特征在于,包括以下步骤:
在玻璃基板上形成栅极与公共电极,所述栅极形成在所述公共电极的一部分上面;
在所述栅极与所述公共电极上形成一层栅极绝缘层;
在所述栅极绝缘层上沉淀一层透明金属氧化物半导体层;
对所述透明金属氧化物半导体层进行一次图案化处理,以形成半导体有源层前体与像素电极前体,并仅使所述半导体有源层前体的中间部分上面有光阻层;
对所述半导体有源层前体的没有所述光阻层的两端及所述像素电极前体进行离子注入处理,以将它们变成透明导体,使所述半导体有源层前体变为半导体有源层,并使所述像素电极前体变为像素电极;以及
在所述半导体有源层上形成源极与漏极。
2.根据权利要求1所述的FFS阵列基板的制造方法,其特征在于,所述步骤还包括,在所述源极、漏极、半导体有源层以及像素电极上形成一层钝化层。
3.根据权利要求1所述的FFS阵列基板的制造方法,其特征在于,所述栅极与公共电极的制作过程为:在所述玻璃基板上依次沉淀一层ITO层与一层金属层,再对所述ITO层与所述金属层进行一次图案化处理,以形成所述栅极与所述公共电极。
4.根据权利要求1所述的FFS阵列基板的制造方法,其特征在于,所述透明金属氧化物半导体的材料为IGZO。
5.根据权利要求1所述的FFS阵列基板的制造方法,其特征在于,所述透明金属氧化物半导体的材料为ITZO。
6.根据权利要求1所述的FFS阵列基板的制造方法,其特征在于,所述离子注入的方式为:对所述半导体有源层前体两端与所述像素电极前体进行等离子体处理。
7.根据权利要求1所述的FFS阵列基板的制造方法,其特征在于,所述离子为H离子或Ar离子。
8.根据权利要求1所述的FFS阵列基板的制造方法,其特征在于,所述的在所述半导体有源层上形成源极与漏极之前,还包括步骤:在所述半导体有源层及所述像素电极上形成一层刻蚀阻挡层,并在所述半导体有源层两端及靠近所述半导体有源层的所述像素电极的一端上对应的所述刻蚀阻挡层形成过孔,使所述半导体有源层两端及靠近所述半导体有源层的所述像素电极的一端暴露出来。
9.根据权利要求1所述的FFS阵列基板的制造方法,其特征在于,所述栅极绝缘层的制作材料为氧化硅或氧化硅与氮化硅的双层膜。
10.根据权利要求1所述的FFS阵列基板的制造方法,其特征在于,所述刻蚀阻挡层的制作材料为氧化硅。
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| CN106098616A (zh) * | 2016-07-26 | 2016-11-09 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法 |
| WO2017166341A1 (zh) * | 2016-03-30 | 2017-10-05 | 深圳市华星光电技术有限公司 | Tft基板的制作方法及制得的tft基板 |
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| CN116018552A (zh) * | 2021-08-24 | 2023-04-25 | 京东方科技集团股份有限公司 | 一种阵列基板及其制备方法、显示装置 |
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Application publication date: 20151118 |