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CN104184544B - A kind of coding/decoding method and device - Google Patents

A kind of coding/decoding method and device Download PDF

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Publication number
CN104184544B
CN104184544B CN201310198818.4A CN201310198818A CN104184544B CN 104184544 B CN104184544 B CN 104184544B CN 201310198818 A CN201310198818 A CN 201310198818A CN 104184544 B CN104184544 B CN 104184544B
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polynomial
error
bytes
service data
adjoint
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CN104184544A (en
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曾纪瑞
王通
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Sanechips Technology Co Ltd
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ZTE Corp
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Priority to PCT/CN2013/090736 priority patent/WO2014187138A1/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1652—Optical Transport Network [OTN]

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)

Abstract

本发明公开了一种解码方法及装置。本发明的解码方法包括：将并行输入的多路业务数据转换为串行业务数据；对所述串行业务数据进行解码处理；将解码后的业务数据按照时隙复用方式输出到后续电路；该方法能够提高解码效率，减少资源消耗。

The invention discloses a decoding method and device. The decoding method of the present invention includes: converting multi-channel service data input in parallel into serial service data; decoding the serial service data; outputting the decoded service data to a subsequent circuit in a time slot multiplexing manner; The method can improve decoding efficiency and reduce resource consumption.

Description

A kind of coding/decoding method and device
Technical field
The present invention relates to optical communication field more particularly to a kind of coding/decoding methods and device.
Background technique
By factors such as the expansion of fixed broadband business, the rise of 3G/LTE mobile Internet, cloud computing/data center's extensive uses It influences, network bandwidth requirements ramp in recent years, and by continual multiplication, this proposes optical transfer network rate and transmission reliability Higher and higher requirement.Generally use forward error correction (forword error correction) technology in optical communications to reduce Signal is reduced with reaching raising signal transmission quality to light device power requirement by the bit error rate caused by transmission Purpose.RS code be in forward error correction through frequently with one of coding mode, correcting random mark mistake and random burst is wrong Miss etc. is highly effective, has been widely applied to the fields such as optic communication, DTV, data storage.
Prior art application RS code generallys use serial decoded method when decoding, then a code word is serial for a code word Processing, a code word 8bit a, it may be assumed that clock cycle can only handle 8bit, and this method low efficiency, data throughput is low, no High-speed transfer can be competent to data handling requirements, be unfavorable for the raising of whole system transmission rate.
In order to improve decoding efficiency, the prior art coding/decoding method parallel using code word, each clock cycle is parallel 2 code words are handled, decoding efficiency and system data throughput increase, but this method is that two code words are simply parallel, is not 2 code words are handled simultaneously from algorithm support, and its its processing capacity for the OTN business of high-speed transfer is clearly inadequate , it is larger to will lead to circuit scale, consumes a large amount of resource.
Summary of the invention
The main technical problem to be solved in the present invention is to provide a kind of coding/decoding method and device can be improved decoding efficiency, Reduce the consumption of resource.
In order to solve the above technical problems, the present invention provides a kind of coding/decoding method, comprising the following steps:
The multi-channel service data inputted parallel are converted into serial traffic data；
Processing is decoded to the serial traffic data；
Decoded business datum is output to subsequent conditioning circuit according to timeslot multiplex mode.
Further, before the multi-channel service that will be inputted parallel is converted to serial traffic further include:
Bit wide processing is carried out to the multi-channel service inputted parallel, each road business bit wide is switched into unified bit wide.
Further, the process being decoded to the serial traffic data includes:
Operation is carried out to the serial traffic data and generates parallel associated polynomial；
According to the parallel associated polynomial generation error position multinomial and wrong amplitude multinomial；
Correction process is carried out to the serial traffic data according to the error location polynomial and wrong amplitude multinomial, Restore original service data.
Further, the process for generating parallel adjoint polynomial to the progress operation of serial traffic data includes:
The associated polynomial that operation generates two bytes is carried out to the serial traffic data；
It is described according to the parallel associated polynomial generation error position multinomial and the wrong polynomial process packet of amplitude It includes:
The error location polynomial and wrong width of two bytes are generated according to the associated polynomial operation of described two bytes It is worth multinomial；
It is described that error correction is carried out to the serial traffic data according to the error location polynomial and wrong amplitude multinomial Processing, the process for restoring original service data include:
Error polynomial and wrong amplitude multinomial to described two bytes carry out operation, obtain the mistake of two bytes Position and error correction corrected value；
Correction process is carried out to the serial traffic data according to the errors present of two bytes and error correction corrected value, is restored Original service data.
Further, the associated polynomial that the serial traffic data are carried out with operation two bytes of generation is specific Process includes:
If the code word of the business datum received is multinomial are as follows: R (x)=rn-1xn-1+rn-2xn-2+…+r1x+r0；
General associated polynomial coefficient is calculated according to the codeword polynome
The associated polynomial coefficient of two bytes, described two words are calculated according to the general associated polynomial coefficient The coefficient of the associated polynomial of section are as follows:
sj=((((rn·αj+rn-1)α2j+rn-2αj+rn-3)α2j+…+(r5αj+r4))α2j+r3αj+r2)α2j+r1αj+r0j=0, 1,2,…,15；
The associated polynomial of two bytes is generated according to the coefficient of the associated polynomial of described two bytes；
The error location polynomial and mistake that two bytes are generated according to the associated polynomial operation of described two bytes Accidentally the polynomial detailed process of amplitude includes:
The associated polynomial of described two bytes is solved equation, error location polynomial and two byte mistakes are calculated Accidentally amplitude multinomial；
If error location polynomial are as follows: Λ (x)=Λ0+Λ1x+Λ2x2+…+Λtxt, according to the error bit solved equation It sets multinomial operation is carried out to the error location polynomial Λ (x) and obtain the error location polynomial of two bytes, described two The error location polynomial of a byte are as follows:
Λ(α2i)=Λ0+Λ1α2i+Λ2α4i+…+Λ8α16i,i=0,1,2,…,127
Λ(α2i+1)=Λ0+Λ1α2i+1+Λ2α4i+2+…+Λ8α16i+8,i=0,1,2,…,127；
The error polynomial to described two bytes and wrong amplitude multinomial carry out operation, obtain two bytes The process of errors present and error correction corrected value includes:
The error polynomial to described two bytes and wrong amplitude multinomial carry out operation, obtain two bytes The process of errors present and error correction corrected value includes:
The errors present that money search obtains two bytes is carried out to the error polynomial of two bytes, while to described two The wrong amplitude multinomial of byte carries out the error correction corrected value that two bytes are calculated in good fortune Buddhist nun.
Further, the business datum inputted parallel is OTUk business datum, wherein k=2e, 3e, 4.
For the purposes of solving above-mentioned technical problem, the present invention also provides a kind of decoding apparatus, comprising: conversion module, Decoder module and output module；
The conversion module is converted for receiving the multi-channel service data inputted parallel, and by the business datum inputted parallel For serial traffic data；
The decoder module is for being decoded processing to the serial traffic data；
The output module is used to decoded business datum being output to subsequent conditioning circuit according to timeslot multiplex mode.
Further, the decoding apparatus further include: bit width conversion module；
The bit width conversion module is for being converted to the multi-channel service data inputted parallel serially in the conversion module Before business datum, bit wide processing is carried out to the multi-channel service data inputted parallel, the bit wide of each road business datum is switched to unite One bit wide.
Further, the decoder module include: associated polynomial generation module, error location polynomial generation module, Mistake amplitude multinomial and correction module；
The syndrome generation module is used to carry out operation to the serial traffic data to generate parallel associated polynomial；
The error location polynomial generation module is used for multinomial according to the parallel associated polynomial generation error position Formula；
The mistake amplitude multinomial generation module is used for according to the raw wrong amplitude multinomial of the parallel associated polynomial；
The correction module is used for according to the error location polynomial and wrong amplitude multinomial to the serial traffic Data carry out correction process, restore original service data.
Further, the syndrome generation module is used to carry out operation to the serial traffic data to generate two bytes Associated polynomial；
The error location polynomial generation module is used to generate two according to the associated polynomial operation of described two bytes The error location polynomial of a byte；
The mistake amplitude multinomial generation module is used to generate two according to the associated polynomial operation of described two bytes The wrong amplitude multinomial of a byte；
The correction module is used to carry out operation to the error polynomial of described two bytes and wrong amplitude multinomial, The errors present and error correction corrected value for obtaining two bytes, according to the errors present of two bytes and error correction corrected value to the string Row business datum carries out correction process, restores original service data.
Further, the syndrome generation module is used to carry out operation to the serial traffic data to generate two bytes The detailed process of associated polynomial include:
If the code word of the business datum received is multinomial are as follows: R (x)=rn-1xn-1+rn-2xn-2+…+r1x+r0；
General associated polynomial coefficient is calculated according to the codeword polynome
The associated polynomial coefficient of two bytes, described two words are calculated according to the general associated polynomial coefficient The coefficient of the associated polynomial of section are as follows:
sj=((((rn·αj+rn-1)α2j+rn-2αj+rn-3)α2j+…+(r5αj+r4))α2j+r3αj+r2)α2j+r1αj+r0j=0, 1,2,…,15；
The associated polynomial of two bytes is generated according to the coefficient of the associated polynomial of described two bytes；
The error location polynomial generation module is used to generate two according to the associated polynomial operation of described two bytes The detailed process of the error location polynomial of a byte includes:
The associated polynomial of described two bytes is solved equation, error location polynomial and two byte mistakes are calculated Accidentally amplitude multinomial；
If error location polynomial are as follows: Λ (x)=Λ0+Λ1x+Λ2x2+…+Λtxt, according to the error bit solved equation It sets multinomial operation is carried out to the error location polynomial Λ (x) and obtain the error location polynomial of two bytes, described two The error location polynomial of a byte are as follows:
Λ(α2i)=Λ0+Λ1α2i+Λ2α4i+…+Λ8α16i,i=0,1,2,…,127
Λ(α2i+1)=Λ0+Λ1α2i+1+Λ2α4i+2+…+Λ8α16i+8,i=0,1,2,…,127；
The correction module is used to carry out the error bit that money search obtains two bytes to the error polynomial of two bytes It sets, while the error correction corrected value that two bytes are calculated in good fortune Buddhist nun is carried out to the wrong amplitude multinomial of described two bytes.
Further, the business datum inputted parallel is OTUk business datum, wherein k=2e, 3e, 4.
The beneficial effects of the present invention are:
The present invention provides a kind of coding/decoding methods and device can be improved decoding efficiency, reduces resource consumption.Wherein this hair Bright coding/decoding method includes: that the multi-channel service data that will be inputted parallel are converted to serial traffic data；To the serial traffic number It is handled according to being decoded；Decoded business datum is output to subsequent conditioning circuit according to timeslot multiplex mode；This method will be parallel The multiplex coding data of input are converted to serial data, make the shared decoding electricity all the way of multichannel incoming traffic using time-division multiplex technology Road improves solution bit rate compared with prior art, saves resource.
Detailed description of the invention
Fig. 1 is a kind of flow diagram for coding/decoding method that the embodiment of the present invention one provides；
Fig. 2 is a kind of parallel-to-serial converter that the embodiment of the present invention one provides；
Fig. 3 is a kind of flow diagram for decoding process that the embodiment of the present invention one provides；
Fig. 4 is the flow diagram for another decoding process that the embodiment of the present invention one provides；
Fig. 5 is a kind of structural schematic diagram of associated polynomial computing circuit provided by Embodiment 2 of the present invention；
Fig. 6 is a kind of operational flowchart of solving key equation provided by Embodiment 2 of the present invention；
Fig. 7 is a kind of structural schematic diagram of the computing circuit of solving key equation provided by Embodiment 2 of the present invention；
Fig. 8 is a kind of structural schematic diagram of money search module provided by Embodiment 2 of the present invention；
Fig. 9 is the structural schematic diagram that a kind of money provided by Embodiment 2 of the present invention searches for subelement Cm；
Figure 10 is the schematic diagram that a kind of good fortune Buddhist nun provided by Embodiment 2 of the present invention calculates；
Figure 11 is the structural schematic diagram for the first decoding apparatus that the embodiment of the present invention three provides；
Figure 12 is the structural schematic diagram for second of decoding apparatus that the embodiment of the present invention three provides；
Figure 13 is the structural schematic diagram for the third decoding apparatus that the embodiment of the present invention three provides；
Figure 14 is a kind of structural schematic diagram for decoding apparatus that the embodiment of the present invention four provides；
Figure 15 is a kind of schematic diagram for zero padding interleaving treatment that the embodiment of the present invention four provides.
Specific embodiment
Below by specific embodiment combination attached drawing, invention is further described in detail.
Embodiment one:
Such as Fig. 1, a kind of coding/decoding method is present embodiments provided, comprising the following steps:
Step 101: the multi-channel service data inputted parallel are converted into serial traffic data；
Step 102: processing is decoded to the serial traffic data；
Step 103: decoded business datum is output to subsequent conditioning circuit according to timeslot multiplex mode.
The multiplex coding business inputted parallel can be converted to serial traffic by the coding/decoding method of the present embodiment, and to serial Business is decoded processing, and exports decoded data using timeslot multiplex mode, and the coding/decoding method of the present embodiment uses Time-division multiplex technology can make multi-channel service data sharing decoding circuit all the way, meet processing high speed business requirement, improve Decoding efficiency and data throughput avoid passing through the mode for increasing decoding circuit to improve decoding efficiency, reduce resource Consumption.A variety of coding business of the coding/decoding method of the present embodiment suitable for optic communication, such as more specification Reed Solomon codes (RS) business.
Serial industry is converted to by the multi-channel service data of coded treatment by what is inputted parallel in the step 101 of the present embodiment Business data can be completed by circuit as shown in Figure 2, for solving RS code, when the three tunnel business inputted parallel, and business difference For OTU1, OTU2, OTU3；The road Tu2Zhong Duige business stores respectively, is such as stored in RAM, when a line has been expired in business datum storage When generate full status signal, be sent into punching circuit, which arbitration circuit determines according to type of service, corresponding memory module RAM state Business is first sent into rear class decoding circuit and is decoded processing all the way, i.e., the process realizes different business parallel-serial conversion.
The coding/decoding method of the present embodiment, before step 101 further include: the multi-channel service inputted parallel is carried out at bit wide Reason, switchs to unified bit wide for each road business bit wide.Such as the OTU1 business bit wide inputted parallel is 32bit, OTU2 service digit Width is 128bit, and OTU3 business is 256bit.OTU1/2 business bit wide is converted to unified 256bit by bit width conversion circuit, so The OTU1/2/3 that bit wide is 256bit is inputted into parallel-to-serial converter parallel afterwards.
The step of being decoded in above-mentioned steps 102 to the serial traffic data include:
Operation is carried out to the serial traffic data and generates parallel associated polynomial；
According to the parallel associated polynomial generation error position multinomial and wrong amplitude multinomial；
Correction process is carried out to the serial traffic data according to the error location polynomial and wrong amplitude multinomial, Restore original service data.
By taking RS is decoded as an example, decoding process is generally divided into following several steps, as shown in Figure 3:
Step 301: being docked to the code word R(x of business datum it) carries out operation and obtains associated polynomial；
Such as it assume that codeword polynome are as follows: R (x)=rn-1xn-1+rn-2xn-2+…+r1x+r0；Codeword polynome is carried out Operation obtains sj, i.e. associated polynomial；
Step 302: to associated polynomial sjIt carries out operation and obtains error location polynomial Λ (x) and wrong amplitude multinomial Ω(x)；
Calculate error polynomial be exactly solve RS code key equation generally use BM iterative algorithm, PGZ algorithm or Euclidean algorithm obtains error location polynomial Λ (x) and mistake amplitude multinomial Ω (x) by solving equation；
Step 303: operation being carried out to error location polynomial Λ (x) and mistake amplitude multinomial Ω (x) and obtains E(x)；
Step 304: correction process being carried out to serial traffic data according to error pattern E (x), restores original service data. RS decoding is to pass through C(x)=R(x)-E (x) corrects data, C(x) it is correct code word after correcting.
As shown in figure 4, decoding algorithm in the present embodiment coding/decoding method can parallel data processing to two bytes into Row decoding, the process being decoded to the data of two bytes include:
Step 401: the associated polynomial that operation generates two bytes is carried out to the serial traffic data；
Step 402: the error location polynomial of two bytes is generated according to the associated polynomial operation of described two bytes With wrong amplitude multinomial；
Step 403: error polynomial and wrong amplitude multinomial to described two bytes carry out operation, obtain two words The errors present and error correction corrected value of section；
Step 404: error correction is carried out to the serial traffic data according to the errors present of two bytes and error correction corrected value Processing restores original service data.
The detailed process that the present embodiment coding/decoding method is decoded two bytes is described below:
In above-mentioned steps 401 the serial traffic data are carried out with the specific of the associated polynomial of operation two bytes of generation Process includes:
If the code word of the business datum received is multinomial are as follows: R (x)=rn-1xn-1+rn-2xn-2+…+r1x+r0；
General associated polynomial coefficient is calculated according to the codeword polynome
The associated polynomial coefficient of two bytes, described two words are calculated according to the general associated polynomial coefficient The coefficient of the associated polynomial of section are as follows:
sj=((((rn·αj+rn-1)α2j+rn-2αj+rn-3)α2j+…+(r5αj+r4))α2j+r3αj+r2)α2j+r1αj+r0j=0, 1,2,…,15；
The associated polynomial of two bytes is generated according to the coefficient of the associated polynomial of described two bytes；
The errors present for generating two bytes according to the associated polynomial operation of described two bytes in above-mentioned steps 402 is more Item formula and the wrong polynomial detailed process of amplitude include:
The associated polynomial of described two bytes is solved equation, error location polynomial and two bytes are calculated Mistake amplitude multinomial；
If error location polynomial are as follows: Λ (x)=Λ0+Λ1x+Λ2x2+…+Λtxt, according to the error bit solved equation It sets multinomial operation is carried out to the error location polynomial Λ (x) and obtain the error location polynomial of two bytes, described two The error location polynomial of a byte are as follows:
Λ(α2i)=Λ0+Λ1α2i+Λ2α4i+…+Λ8α16i,i=0,1,2,…,127
Λ(α2i+1)=Λ0+Λ1α2i+1+Λ2α4i+2+…+Λ8α16i+8,i=0,1,2,…,127；
Operation is carried out to the error polynomial of described two bytes and wrong amplitude multinomial in above-mentioned steps 403, is obtained The errors present of two bytes and the process of error correction corrected value include:
The errors present that money search obtains two bytes is carried out to the error polynomial of two bytes, while to described two The wrong amplitude multinomial of byte carries out the error correction corrected value that two bytes are calculated in good fortune Buddhist nun.
The coding/decoding method of the present embodiment is suitable for the decoding to OTUk business datum, wherein k=2e, 3e, 4.
The coding/decoding method of the present embodiment can be decoded processing to the data of two bytes simultaneously, compared with prior art Substantially increase decoding efficiency.
Carrying out RS decoding using the coding/decoding method of the present embodiment has effect below:
(1) larger using circuit scale when single channel decoding circuit parallel mode processing multi-channel service.When the business road of processing When number is more, such as there is decoding circuit all the way per business all the way, then entire circuit scale is very big, and the resource of consumption is quite a few.? It is that can save resource using coding/decoding method of the invention the problem of must be taken into consideration that resource consumption is reduced on implementation.
(2) for OTN business, 100G processing is development trend, and chip must also have such processing capacity, and RS decoding circuit does not have such processing capacity still at present.It is parallel to improve OTN business by exploitation new algorithm for the method for the present invention Processing capacity has reached the requirement of 100G business processing.
(3) the OTU(Optical Channel Transport Unit specified in the G.709 agreement) for frame format, Using parallel decoding method of the invention, each clock can handle at least two code word, and decoding efficiency improves at least 1 times；
(4) by taking OTU frame format as an example, data throughput of the serial coding/decoding method of the RS of the prior art under 456MHz clock For 58.368Gbps, and use two code word parallel decoding mode throughputs for 116.736Gbps.Data throughput further mentions Height, it is very helpful for the promotion of transmission network rate, meet 100G rate business processing requirement.
Embodiment two:
The present embodiment is discussed in detail to two decoded algorithms of byte parallel, and the bit wide of the business datum inputted parallel is 256bit:
Step 1: parallel syndrome calculates；
If the codeword polynome of the business datum received are as follows: R (x)=rn-1xn-1+rn-2xn-2+…+r1x+r0, by business number According to codeword polynome calculate general syndrome multinomial coefficient sjCalculation method, the calculating of the syndrome coefficient can be by Computing circuit shown in fig. 5 is completed:
Wherein, j=0,1,2, Xi, 15,
To general syndrome multinomial coefficient sjAlgorithm development is carried out, the associated polynomial coefficient of two bytes is obtained, The associated polynomial coefficient are as follows:
sj=((((rn·αj+rn-1)α2j+rn-2αj+rn-3)α2j+…+(r5αj+r4))α2j+r3αj+r2)α2j+r1αj+r0j=0, 1,2,…,15；
The associated polynomial coefficient of last two bytes calculated constructs corresponding associated polynomial.
Step 2: solving key equation；
The purpose of solving key equation is by the syndrome polynomial computation error location polynomial of two bytes of the first step With wrong amplitude multinomial；Wherein wrong amplitude multinomial is the wrong amplitude multinomial Ω (x) of two bytes；
Solving key equation can use RIBM algorithm, and specific calculating process can refer to Fig. 6；
The computing circuit of the concrete operation circuit of solving key equation as shown in Figure 7 is realized, in Fig. 7 under control unit control The interative computation for carrying out for 16 periods completes solving key equation process.Calculate error location polynomial and wrong amplitude system of polynomials Number.Error location polynomial and wrong amplitude multinomial can be obtained in the present embodiment using the algorithm of any maturation.
Step 3: being transported after calculating error location polynomial to the calculated error location polynomial of second step It calculates and derives, the process of algorithm development is as follows:
If error location polynomial are as follows: Λ (x)=Λ0+Λ1x+Λ2x2+…+Λtxt, solved equation according to second step Error location polynomial carries out algorithm development to the error location polynomial Λ (x), is derived from the error bit of two bytes Set multinomial Λ (x):
Λ(α2i)=Λ0+Λ1α2i+Λ2α4i+…+Λ8α16i,i=0,1,2,…,127
Λ(α2i+1)=Λ0+Λ1α2i+1+Λ2α4i+2+…+Λ8α16i+8,i=0,1,2,…,127
Step 4: calculated according to error location polynomial Λ (x) and mistake amplitude multinomial Ω (x) obtain errors present with Error correction corrected value；
The errors present of two bytes, specific money search process are obtained using money search to above-mentioned error location polynomial Module is completed as shown in Figure 8, is as depicted in figure 8 the parallel money search module structural schematic diagram of two-way；Money search wherein in Fig. 8 is single The structural schematic diagram of first Cm is as shown in Figure 9；
The error correction corrected value that two bytes are calculated in good fortune Buddhist nun, error correction correction are carried out to above-mentioned wrong amplitude multinomial simultaneously It is worth the formula calculated are as follows: ex=(x16Ω (x))/(x Λ ' (x)), Λ ' (x) is the derived function of Λ (x), the even power of Λ (x) The derivative for the odd times power that derivative is zero, Λ (x) is Λodd(x)/x；The process that specific good fortune Buddhist nun calculates refers to Figure 10.
Step 4: generating the error pattern E (x) of two bytes according to calculated errors present and error correction corrected value；
Step 5: carrying out two byte error correction according to serial traffic data of the error pattern E (x) of two bytes to output Processing restores the business datum of original two bytes；
Particular by C(x)=R(x)-E (x) this formula corrects data, C(x) it is correct code after correcting Word.
Embodiment three:
As shown in figure 11, a kind of decoding apparatus is present embodiments provided, comprising: conversion module, decoder module and output mould Block；
The conversion module is converted for receiving the multi-channel service data inputted parallel, and by the business datum inputted parallel For serial traffic data；
The decoder module is for being decoded processing to the serial traffic data；
The output module is used to decoded business datum being output to subsequent conditioning circuit according to timeslot multiplex mode.
As shown in figure 12, the decoding apparatus of the present embodiment can also include: bit width conversion module；
The bit width conversion module is for being converted to the multi-channel service data inputted parallel serially in the conversion module Before business datum, bit wide processing is carried out to the multi-channel service data inputted parallel, the bit wide of each road business datum is switched to unite One bit wide.
As shown in figure 13, decoder module provided in this embodiment may include: associated polynomial generation module, errors present Multinomial generation module, mistake amplitude multinomial and correction module；
The syndrome generation module is used to carry out operation to the serial traffic data to generate parallel associated polynomial；
The error location polynomial generation module is used for multinomial according to the parallel associated polynomial generation error position Formula；
The mistake amplitude multinomial generation module is used for according to the raw wrong amplitude multinomial of the parallel associated polynomial；
The correction module is used for according to the error location polynomial and wrong amplitude multinomial to the serial traffic Data carry out correction process, restore original service data.
In another application scenarios, the decoding apparatus of the present embodiment can the business datum to two bytes located parallel Reason, the function of each module in the present embodiment in decoder module is as follows at this time:
Syndrome generation module is used to carry out the associated polynomial that operation generates two bytes to the serial traffic data；
Error location polynomial generation module is used to generate two words according to the associated polynomial operation of described two bytes The error location polynomial of section；
Mistake amplitude multinomial generation module is used to generate two words according to the associated polynomial operation of described two bytes The wrong amplitude multinomial of section；
Correction module is used to carry out operation to the error polynomial of described two bytes and wrong amplitude multinomial, obtains two The errors present and error correction corrected value of a byte, according to the errors present of two bytes and error correction corrected value to the serial traffic Data carry out correction process, restore original service data.
The present embodiment decoding apparatus is described below specifically to locate each module of the business datum parallel decoding of two bytes Reason process:
The syndrome generation module is used to carry out the serial traffic data operation and generates the adjoint more of two bytes The detailed process of formula includes:
If the code word of the business datum received is multinomial are as follows: R (x)=rn-1xn-1+rn-2xn-2+…+r1x+r0；
General associated polynomial coefficient is calculated according to the codeword polynome
The associated polynomial coefficient of two bytes, described two words are calculated according to the general associated polynomial coefficient The coefficient of the associated polynomial of section are as follows:
sj=((((rn·αj+rn-1)α2j+rn-2αj+rn-3)α2j+…+(r5αj+r4))α2j+r3αj+r2)α2j+r1αj+r0 j= 0,1,2,…,15；
The associated polynomial of two bytes is generated according to the coefficient of the associated polynomial of described two bytes；
The error location polynomial generation module is used to generate two according to the associated polynomial operation of described two bytes The detailed process of the error location polynomial of a byte includes:
The associated polynomial of described two bytes is solved equation, error location polynomial and two byte mistakes are calculated Accidentally amplitude multinomial；
If error location polynomial are as follows: Λ (x)=Λ0+Λ1x+Λ2x2+…+Λtxt, according to the error bit solved equation It sets multinomial operation is carried out to the error location polynomial Λ (x) and obtain the error location polynomial of two bytes, described two The error location polynomial of a byte are as follows:
Λ(α2i)=Λ0+Λ1α2i+Λ2α4i+…+Λ8α16i,i=0,1,2,…,127
Λ(α2i+1)=Λ0+Λ1α2i+1+Λ2α4i+2+…+Λ8α16i+8,i=0,1,2,…,127；
The correction module is used to carry out the error bit that money search obtains two bytes to the error polynomial of two bytes It sets, while the error correction corrected value that two bytes are calculated in good fortune Buddhist nun is carried out to the wrong amplitude multinomial of described two bytes.
The specific operation process for the decoding apparatus that the present embodiment mentions can refer to the above-mentioned description to coding/decoding method, such as With reference to the description of Fig. 2,4,5,6,7,8,9,10.
Through the above description, it can be seen that the multiplex coding business that the decoding apparatus of the present embodiment will can input parallel Serial traffic is converted to, and processing is decoded to serial traffic, and decoded data are exported using timeslot multiplex mode, this The decoding apparatus of embodiment uses time-division multiplex technology, can make multi-channel service data sharing decoding circuit all the way, meets The requirement of processing high speed business, improves decoding efficiency and data throughput, avoids passing through and increases decoding circuit to improve decoding The mode of efficiency reduces the consumption of resource.A variety of coding business of the decoding apparatus of the present embodiment suitable for optic communication, example Such as more specification Reed Solomon code (RS) business.The decoding apparatus of the present embodiment applies also for solving OTUk business datum Code, wherein k=2e, 3e, 4.
Example IV:
As shown in figure 14, another decoding apparatus is present embodiments provided, increases caching mould on the basis of implementing three Block, zero padding interleaving block, zero-suppress de-interleaving block；
The zero padding interleaving block is used to carry out zero padding interleaving treatment to serial traffic data before being decoded, after obtaining Grade operation is all the integer clock cycle；When to bit wide is that 256bitOTU business carries out RS decoding, the process of zero padding processing With reference to Figure 15；
Cache module is used to cache the serial traffic data Jing Guo zero padding interleaving treatment；It can be FIFO first in first out Buffer；
The de-interleaving block that zero-suppresses keeps its extensive for carrying out deinterleaving processing of zero-suppressing to the business datum after correction process It is again the business datum of unprocessed form.Such as original OTN frame format can be reverted to.
It is described in detail below and the decoded process of RS is carried out to three road OUT business using the present embodiment decoding apparatus:
Step 1: the OTU2 business bit wide inputted parallel is 32bit, and OTU3 business bit wide is 128bit, and OTU4 business is 256bit.OTU2/3 business bit wide is converted to unified 256bit by bit width conversion circuit.
Step 2: each road business of 256bit bit wide is stored in RAM, and the full status signal of row is generated when having expired a line, It is sent into arbitration circuit；Arbitration circuit determines which business is first sent into rear class algorithm circuit according to type of service, corresponding RAM state Processing, is shown in Fig. 2.This step completes different business parallel-serial conversion.
Step 3: into the carry out business decoding process of algorithm circuit.Zero padding interleaving treatment is carried out first.At zero padding Reason is shown in Figure 15, so that rear class operation is all the integer clock cycle, the data after intertexture send to cache module caching for example all the way Fifo buffer sends to algorithm operation all the way.
Step 4: business datum is sent into syndrome generation module, structural reference Fig. 5 of the module after zero padding interweaves.
The syndrome operation is the 2 byte parallel mathematical algorithms based on innovation, in OTN frame structure 16 code blocks simultaneously into Row operation, each code block calculate 2 bytes simultaneously.
Step 5: error polynomial generation module and wrong amplitude multinomial generation module use RiBM algorithm solution key side Journey；
The interative computation for carrying out for 16 periods under control unit control as shown in Figure 7 completes solving key equation process.It calculates Make mistake position multinomial and error value multinomial coefficient.
Step 6: the search of errors present is completed in money search according to error location polynomial, and circuit is aforementioned according to this use-case The design of money searching algorithm formula is innovated, two byte search operations can be completed at the same time, see Fig. 8.
Step 7: it is that good fortune Buddhist nun calculating is carried out according to wrong amplitude multinomial simultaneously with step 6, calculates two words Good fortune Buddhist nun's error correction corrected value of section.Detailed process is shown in Figure 10.
Step 8: correction module calculates the data bit that mistake occurs in the data of cache module output using money search It sets, again according to the calculated corrected value of good fortune Buddhist nun
Step 9: according to errors present and corrected value generation error pattern, number is exported to caching fifo according to error pattern Two byte corrections are carried out according to the bit of corresponding position.
Step 10: the business datum by correction process is sent into the de-interleaving block that zero-suppresses and reverts to OTN frame format.
Step 11: each business datum is output to late-class circuit according to timeslot multiplex mode.
Carrying out RS decoding using the decoding apparatus of the present embodiment has effect below:
(1) larger using circuit scale when single channel decoding circuit parallel mode processing multi-channel service.When the business road of processing When number is more, such as there is decoding circuit all the way per business all the way, then entire circuit scale is very big, and the resource of consumption is quite a few.? It is that can save resource using coding/decoding method of the invention the problem of must be taken into consideration that resource consumption is reduced on implementation.
(2) for OTN business, 100G processing is development trend, and chip must also have such processing capacity, And RS decoding circuit does not have such processing capacity still at present.The method of the present invention improves OTN business simultaneously by exploitation new algorithm Row processing capacity has reached the requirement of 100G business processing.
(3) the OTU(Optical Channel Transport Unit specified in the G.709 agreement) for frame format, Using parallel decoding method of the invention, each clock can handle at least two code word, and decoding efficiency improves at least 1 times；
(4) by taking OTU frame format as an example, data throughput of the serial coding/decoding method of the RS of the prior art under 456MHz clock For 58.368Gbps, and use two code word parallel decoding mode throughputs for 116.736Gbps.Data throughput further mentions Height, it is very helpful for the promotion of transmission network rate, meet 100G rate business processing requirement.
The above content is specific embodiment is combined, further detailed description of the invention, and it cannot be said that this hair Bright specific implementation is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, it is not taking off Under the premise of from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to protection of the invention Range.

Claims (12)

1.一种解码方法，其特征在于，包括以下步骤：1. a decoding method, is characterized in that, comprises the following steps: 将并行输入的多路不同业务类型的业务数据转换为一路串行业务数据；Convert multiple channels of business data of different business types input in parallel into one channel of serial business data; 通过一路解码电路对所述串行业务数据中的多路业务数据依次进行解码处理；Perform decoding processing on the multi-channel service data in the serial service data sequentially through a channel of decoding circuit; 将解码后的业务数据按照时隙复用方式输出到后续电路。The decoded service data is output to subsequent circuits in a time-slot multiplexing manner. 2.如权利要求1所述的解码方法，其特征在于，在所述将并行输入的多路不同业务类型的业务转换为一路串行业务之前还包括：2. The decoding method as claimed in claim 1, further comprising: 对并行输入的多路业务进行位宽处理，将各路业务位宽转为统一的位宽。The bit width processing is performed on the multi-channel services input in parallel, and the bit width of each channel is converted into a unified bit width. 3.如权利要求1或2所述的解码方法，其特征在于，所述通过一路解码电路对所述串行业务数据中的多路业务数据依次进行解码的过程包括：3. The decoding method according to claim 1 or 2, wherein the process of sequentially decoding the multi-channel service data in the serial service data through a decoding circuit comprises: 对所述串行业务数据进行运算生成并行伴随多项式；performing operations on the serial service data to generate parallel adjoint polynomials; 根据所述并行伴随多项式生成错误位置多项式和错误幅值多项式；generating an error location polynomial and an error magnitude polynomial from the parallel adjoint polynomial; 根据所述错误位置多项式和错误幅值多项式对所述串行业务数据进行纠错处理，恢复原始业务数据。Perform error correction processing on the serial service data according to the error position polynomial and the error amplitude polynomial to restore the original service data. 4.如权利要求3所述的解码方法，其特征在于，所述对串行业务数据进行运算生成并行伴随多项的过程包括：4. decoding method as claimed in claim 3, is characterized in that, the described process that the serial service data is operated to generate parallel concomitant multinomial comprises: 对所述串行业务数据进行运算生成两个字节的伴随多项式，所述并行伴随多项式由所述两个字节的伴随多项式构成；performing an operation on the serial service data to generate a two-byte adjoint polynomial, and the parallel adjoint polynomial is composed of the two-byte adjoint polynomial; 所述根据所述并行伴随多项式生成错误位置多项式和错误幅值多项式的过程包括：The process of generating an error location polynomial and an error magnitude polynomial according to the parallel adjoint polynomial includes: 根据所述两个字节的伴随多项式运算生成两个字节的错误位置多项式和错误幅值多项式；generating a two-byte error position polynomial and an error magnitude polynomial according to the adjoint polynomial operation of the two bytes; 所述根据所述错误位置多项式和错误幅值多项式对所述串行业务数据进行纠错处理，恢复原始业务数据的过程包括：The process of performing error correction processing on the serial service data according to the error position polynomial and the error amplitude polynomial, and restoring the original service data includes: 对所述两个字节的错误位置多项式和错误幅值多项式进行运算，获取两个字节的错误位置和纠错校正值；Perform operation on the error position polynomial and the error amplitude polynomial of the two bytes to obtain the error position and error correction correction value of the two bytes; 根据两个字节的错误位置和纠错校正值对所述串行业务数据进行纠错处理，恢复原始业务数据。Perform error correction processing on the serial service data according to the error position of the two bytes and the error correction correction value, and restore the original service data. 5.如权利要求4所述的解码方法，其特征在于，应用于RS解码，所述对所述串行业务数据进行运算生成两个字节的伴随多项式的具体过程包括：5. The decoding method according to claim 4, wherein, when applied to RS decoding, the specific process of performing an operation on the serial service data to generate an adjoint polynomial of two bytes comprises: 设接收到的业务数据的码字多项式为：R(x)＝rn_1xn-1+rn_2xn-2+…+r1x+r0，所述r为接收的字符，所述n为接收字符的位置，所述x为所述位置接收的值是否为真；Let the codeword polynomial of the received service data be: R(x)=r n_1 x n-1 +r n_2 x n-2 +...+r 1 x+r 0 , the r is the received character, the n is the position of the received character, and the x is whether the value received by the position is true; 根据所述码字多项式计算出通用的伴随多项式系数A general adjoint polynomial coefficient is calculated from the codeword polynomial 所述n为接收字符的位置，所述α为本原元素； The n is the position of the received character, and the α is the original element; 根据所述通用的伴随多项式系数计算出两个字节的伴随多项式系数，所述两个字节的伴随多项式的系数为：Two-byte adjoint polynomial coefficients are calculated according to the general adjoint polynomial coefficients, and the coefficients of the two-byte adjoint polynomial are: 所述α为本原元素，所述r为接收的字符； The α is the original element, and the r is the received character; 根据所述两个字节的伴随多项式的系数生成两个字节的伴随多项式；generating a two-byte adjoint polynomial from the coefficients of the two-byte adjoint polynomial; 所述根据所述两个字节的伴随多项式运算生成两个字节的错误位置多项式和错误幅值多项式的具体过程包括:The specific process of generating the error position polynomial and the error amplitude polynomial of the two bytes according to the adjoint polynomial operation of the two bytes includes: 对所述两个字节的伴随多项式进行解方程，计算出错误位置多项式和两个字节错误幅值多项式；Solve the equation for the adjoint polynomial of the two bytes, and calculate the error position polynomial and the two-byte error amplitude polynomial; 设错误位置多项式为：Λ(x)＝Λ0+Λ1x+Λ2x2+…+Λtxt，所述Λ为错误位置，所述t为纠错能力，根据解方程得到的错误位置多项式对所述错误位置多项式Λ(x)进行运算得到两个字节的错误位置多项式，所述两个字节的错误位置多项式为：Let the error position polynomial be: Λ(x)=Λ 0 +Λ 1 x+Λ 2 x 2 +...+Λ t x t , the Λ is the error position, and the t is the error correction ability, obtained according to the solution equation The error location polynomial operates on the error location polynomial Λ(x) to obtain the error location polynomial of two bytes, and the error location polynomial of the two bytes is: Λ(α2i)＝Λ0+Λ1α2i+Λ2α4i+…+Λ8α16i,i＝0,1,2,…,127Λ(α 2i )=Λ 0 +Λ 1 α 2i +Λ 2 α 4i +...+Λ 8 α 16i , i=0,1,2,...,127 Λ(α2i+1)＝Λ0+Λ1α2i+1+Λ2α4i+2+…+Λ8α16i+8,i＝0,1,2,…,127，所述Λ为错误位置，所述α为本原元素；Λ(α 2i+1 )=Λ 0 +Λ 1 α 2i+1 +Λ 2 α 4i+2 +...+Λ 8 α 16i+8 , i=0,1,2,...,127, the Λ is Error position, the α is the original element; 所述对所述两个字节的错误位置多项式和错误幅值多项式进行运算，获取两个字节的错误位置和纠错校正值的过程包括：The process of operating the error position polynomial and the error amplitude polynomial of the two bytes, and obtaining the error position and error correction value of the two bytes includes: 对两个字节的错误位置多项式进行钱搜索获取两个字节的错误位置，同时对所述两个字节的错误幅值多项式进行福尼计算得到两个字节的纠错校正值。Perform a money search on the error position polynomial of the two bytes to obtain the error position of the two bytes, and at the same time perform Forney calculation on the error amplitude polynomial of the two bytes to obtain the error correction value of the two bytes. 6.如权利要求5所述的解码方法，其特征在于，所述并行输入的业务数据为OTUk业务数据，其中k＝2e、3e、4。6 . The decoding method according to claim 5 , wherein the service data input in parallel is OTUk service data, wherein k=2e, 3e, and 4. 7 . 7.一种解码装置，其特征在于，包括：转换模块、解码模块和输出模块；7. A decoding device, comprising: a conversion module, a decoding module and an output module; 所述转换模块用于接收并行输入的多路不同业务类型的业务数据，并将并行输入的业务数据转换为一路串行业务数据；The conversion module is used for receiving multiple channels of business data of different business types input in parallel, and converting the business data input in parallel into one channel of serial business data; 所述解码模块用于通过一路解码电路对所述串行业务数据的多路业务数据依次进行解码处理；The decoding module is used to sequentially decode and process the multi-channel service data of the serial service data through a decoding circuit; 所述输出模块用于将解码后的业务数据按照时隙复用方式输出到后续电路。The output module is used for outputting the decoded service data to a subsequent circuit in a time-slot multiplexing manner. 8.如权利要求7所述的解码装置，其特征在于，所述解码装置还包括：位宽转换模块；8. The decoding device according to claim 7, wherein the decoding device further comprises: a bit width conversion module; 所述位宽转换模块用于在所述转换模块将并行输入的多路不同业务类型的业务数据转换为一路串行业务数据之前，对并行输入的多路业务数据进行位宽处理，将各路业务数据的位宽转为统一的位宽。The bit-width conversion module is used to perform bit-width processing on the parallel-input multi-channel service data before the conversion module converts the parallel-input multi-channel service data of different service types into one-channel serial service data, and converts each channel of service data into one channel. The bit width of the service data is changed to a uniform bit width. 9.如权利要求7或8所述的解码装置，其特征在于，所述解码模块包括：伴随多项式产生模块、错误位置多项式产生模块、错误幅值多项式和纠错模块；9. The decoding apparatus according to claim 7 or 8, wherein the decoding module comprises: an adjoint polynomial generation module, an error location polynomial generation module, an error amplitude polynomial and an error correction module; 所述伴随式产生模块用于对所述串行业务数据进行运算生成并行伴随多项式；The syndrome generating module is configured to perform operations on the serial service data to generate parallel syndrome polynomials; 所述错误位置多项式产生模块用于根据所述并行伴随多项式生成错误位置多项式；The error location polynomial generating module is configured to generate an error location polynomial according to the parallel adjoint polynomial; 所述错误幅值多项式产生模块用于根据所述并行伴随多项式生错误幅值多项式；The error magnitude polynomial generating module is configured to generate an error magnitude polynomial according to the parallel adjoint polynomial; 所述纠错模块用于根据所述错误位置多项式和错误幅值多项式对所述串行业务数据进行纠错处理，恢复原始业务数据。The error correction module is configured to perform error correction processing on the serial service data according to the error position polynomial and the error amplitude polynomial to restore the original service data. 10.如权利要求9所述的解码装置，其特征在于，所述伴随式产生模块用于对所述串行业务数据进行运算生成两个字节的伴随多项式，所述并行伴随多项式由所述两个字节的伴随多项式构成；10. The decoding device according to claim 9, wherein the syndrome generating module is configured to perform an operation on the serial service data to generate a two-byte syndrome polynomial, and the parallel syndrome polynomial is determined by the Two-byte adjoint polynomial composition; 所述错误位置多项式产生模块用于根据所述两个字节的伴随多项式运算生成两个字节的错误位置多项式；The error location polynomial generating module is configured to generate a two-byte error location polynomial according to the adjoint polynomial operation of the two bytes; 所述错误幅值多项式产生模块用于根据所述两个字节的伴随多项式运算生成两个字节的错误幅值多项式；The error amplitude polynomial generating module is configured to generate a two-byte error amplitude polynomial according to the adjoint polynomial operation of the two bytes; 所述纠错模块用于对所述两个字节的错误位置多项式和错误幅值多项式进行运算，获取两个字节的错误位置和纠错校正值，根据两个字节的错误位置和纠错校正值对所述串行业务数据进行纠错处理，恢复原始业务数据。The error correction module is used to operate on the error position polynomial and the error amplitude polynomial of the two bytes to obtain the error position and error correction correction value of the two bytes, according to the error position and correction value of the two bytes. The error correction value performs error correction processing on the serial service data to restore the original service data. 11.如权利要求10所述的解码装置，其特征在于，应用于RS解码，11. The decoding apparatus according to claim 10, wherein, when applied to RS decoding, 所述伴随式产生模块用于对所述串行业务数据进行运算生成两个字节的伴随多项式的具体过程包括：The specific process that the syndrome generating module is used to perform operations on the serial service data to generate a two-byte syndrome polynomial includes: 设接收到的业务数据的码字多项为：R(x)＝rn-1xn-1+rn-2xn-2+…+r1x+r0，所述r为接收的字符，所述n为接收字符的位置，所述x为所述位置接收的值是否为真；Let the codeword polynomial of the received service data be: R(x)=r n-1 x n-1 +r n-2 x n-2 +...+r 1 x+r 0 , the r is the received character, the n is the position of the received character, and the x is whether the value received at the position is true; 根据所述码字多项式计算出通用的伴随多项式系数所述n为接收字符的位置，所述α为本原元素；A general adjoint polynomial coefficient is calculated from the codeword polynomial The n is the position of the received character, and the α is the original element; 根据所述通用的伴随多项式系数计算出两个字节的伴随多项式系数，所述两个字节的伴随多项式的系数为：Two-byte adjoint polynomial coefficients are calculated according to the general adjoint polynomial coefficients, and the coefficients of the two-byte adjoint polynomial are: 所述α为本原元素，所述r为接收的字符； The α is the original element, and the r is the received character; 根据所述两个字节的伴随多项式的系数生成两个字节的伴随多项式；generating a two-byte adjoint polynomial from the coefficients of the two-byte adjoint polynomial; 所述错误位置多项式产生模块用于根据所述两个字节的伴随多项式运算生成两个字节的错误位置多项式的具体过程包括：The specific process that the error location polynomial generating module is used to generate the error location polynomial of two bytes according to the adjoint polynomial operation of the two bytes includes: 对所述两个字节的伴随多项式进行解方程，计算出错误位置多项式和两个字节错误幅值多项式；Solve the equation for the adjoint polynomial of the two bytes, and calculate the error position polynomial and the two-byte error amplitude polynomial; 设错误位置多项式为：Λ(x)＝Λ0+Λ1x+Λ2x2+…+Λtxt，所述Λ为错误位置，所述t为纠错能力，根据解方程得到的错误位置多项式对所述错误位置多项式Λ(x)进行运算得到两个字节的错误位置多项式，所述两个字节的错误位置多项式为：Let the error position polynomial be: Λ(x)=Λ 0 +Λ 1 x+Λ 2 x 2 +...+Λ t x t , the Λ is the error position, and the t is the error correction ability, obtained according to the solution equation The error location polynomial operates on the error location polynomial Λ(x) to obtain the error location polynomial of two bytes, and the error location polynomial of the two bytes is: Λ(α2i)＝Λ0+Λ1α2i+Λ2α4i+…+Λ8α16i,i＝0,1,2,…,127Λ(α 2i )=Λ 0 +Λ 1 α 2i +Λ 2 α 4i +...+Λ 8 α 16i , i=0,1,2,...,127 Λ(α2i+1)＝Λ0+Λ1α2i+1+Λ2α4i+2+…+Λ8α16i+8,i＝0,1,2,…,127，所述Λ为错误位置，所述α为本原元素；Λ(α 2i+1 )=Λ 0 +Λ 1 α 2i+1 +Λ 2 α 4i+2 +...+Λ 8 α 16i+8 , i=0,1,2,...,127, the Λ is Error position, the α is the original element; 所述纠错模块用于对两个字节的错误位置多项式进行钱搜索获取两个字节的错误位置，同时对所述两个字节的错误幅值多项式进行福尼计算得到两个字节的纠错校正值。The error correction module is used to perform a money search on the error position polynomial of the two bytes to obtain the error position of the two bytes, and at the same time, perform the Forney calculation on the error amplitude polynomial of the two bytes to obtain the two bytes. error correction correction value. 12.如权利要求11所述的解码装置，其特征在于，所述并行输入的业务数据为OTUk业务数据，其中k＝2e、3e、4。12 . The decoding apparatus according to claim 11 , wherein the service data input in parallel is OTUk service data, where k=2e, 3e, and 4. 13 .
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