AT505203A5 - Instruction cache für echtzeitsysteme - Google Patents
Instruction cache für echtzeitsysteme Download PDFInfo
- Publication number
- AT505203A5 AT505203A5 AT0932505A AT93252005A AT505203A5 AT 505203 A5 AT505203 A5 AT 505203A5 AT 0932505 A AT0932505 A AT 0932505A AT 93252005 A AT93252005 A AT 93252005A AT 505203 A5 AT505203 A5 AT 505203A5
- Authority
- AT
- Austria
- Prior art keywords
- real
- instruction cache
- time systems
- systems
- time
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30054—Unconditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4482—Procedural
- G06F9/4484—Executing subprograms
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AT0932505A AT505203A5 (de) | 2004-08-17 | 2005-08-12 | Instruction cache für echtzeitsysteme |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AT0138304A AT500858B8 (de) | 2004-08-17 | 2004-08-17 | Instruction cache für echtzeitsysteme |
| AT0932505A AT505203A5 (de) | 2004-08-17 | 2005-08-12 | Instruction cache für echtzeitsysteme |
| PCT/AT2005/000326 WO2006017874A2 (de) | 2004-08-17 | 2005-08-12 | Befehls-cachespeicher für echtzeitsysteme |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AT505203A5 true AT505203A5 (de) | 2008-11-15 |
Family
ID=35134456
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT0138304A AT500858B8 (de) | 2004-08-17 | 2004-08-17 | Instruction cache für echtzeitsysteme |
| AT0932505A AT505203A5 (de) | 2004-08-17 | 2005-08-12 | Instruction cache für echtzeitsysteme |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT0138304A AT500858B8 (de) | 2004-08-17 | 2004-08-17 | Instruction cache für echtzeitsysteme |
Country Status (2)
| Country | Link |
|---|---|
| AT (2) | AT500858B8 (de) |
| WO (1) | WO2006017874A2 (de) |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4755935A (en) * | 1986-01-27 | 1988-07-05 | Schlumberger Technology Corporation | Prefetch memory system having next-instruction buffer which stores target tracks of jumps prior to CPU access of instruction |
| JPH01205228A (ja) * | 1988-02-10 | 1989-08-17 | Hitachi Ltd | 命令バツフアシステム |
| US5490262A (en) * | 1989-09-01 | 1996-02-06 | Oki Electric Industry Co., Ltd. | Dual cache memory device with cache monitoring |
| GB9118312D0 (en) * | 1991-08-24 | 1991-10-09 | Motorola Inc | Real time cache implemented by dual purpose on-chip memory |
| US5353425A (en) * | 1992-04-29 | 1994-10-04 | Sun Microsystems, Inc. | Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature |
| US5974534A (en) * | 1994-02-14 | 1999-10-26 | Hewlett-Packard Company | Predecoding and steering mechanism for instructions in a superscalar processor |
| WO1997036234A1 (en) * | 1996-03-28 | 1997-10-02 | International Business Machines Corporation | Cache multi-block touch mechanism for object oriented computer system |
| US5893142A (en) * | 1996-11-14 | 1999-04-06 | Motorola Inc. | Data processing system having a cache and method therefor |
| US5913224A (en) * | 1997-02-26 | 1999-06-15 | Advanced Micro Devices, Inc. | Programmable cache including a non-lockable data way and a lockable data way configured to lock real-time data |
| US6157981A (en) * | 1998-05-27 | 2000-12-05 | International Business Machines Corporation | Real time invariant behavior cache |
| US7143268B2 (en) * | 2000-12-29 | 2006-11-28 | Stmicroelectronics, Inc. | Circuit and method for instruction compression and dispersal in wide-issue processors |
| DE10204345A1 (de) * | 2002-02-01 | 2003-08-14 | Systemonic Ag | Verfahren zur Befehlsbearbeitung |
-
2004
- 2004-08-17 AT AT0138304A patent/AT500858B8/de not_active IP Right Cessation
-
2005
- 2005-08-12 AT AT0932505A patent/AT505203A5/de not_active Application Discontinuation
- 2005-08-12 WO PCT/AT2005/000326 patent/WO2006017874A2/de active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| AT500858B8 (de) | 2007-02-15 |
| WO2006017874A3 (de) | 2006-11-23 |
| AT500858A4 (de) | 2006-04-15 |
| AT500858B1 (de) | 2006-04-15 |
| WO2006017874A2 (de) | 2006-02-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| REJ | Rejection |
Effective date: 20160515 |