Shrivastava et al., 2016 - Google Patents
Automatic management of Software Programmable Memories in Many‐core ArchitecturesShrivastava et al., 2016
View PDF- Document ID
- 359215749086321351
- Author
- Shrivastava A
- Dutt N
- Cai J
- Shoushtari M
- Donyanavard B
- Tajik H
- Publication year
- Publication venue
- IET Computers & Digital Techniques
External Links
Snippet
Software Programmable Memories, or SPMs, are raw on‐chip memories that are not implicitly managed by the processor hardware, but explicitly by software. For example, while caches fetch data from memories automatically and maintain coherence with other caches …
- 230000015654 memory 0 title abstract description 171
Classifications
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- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
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- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
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