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Tahar et al., 1998 - Google Patents

A practical methodology for the formal verification of RISC processors

Tahar et al., 1998

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Document ID
17177570084236213931
Author
Tahar S
Kumar R
Publication year
Publication venue
Formal Methods in System Design

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Snippet

In this paper a practical methodology for formally verifying RISC cores is presented. Using a hierarchical model which reflects the abstraction levels used by designers of real RISC processors, proofs between neighboring levels are performed for simplifying the verification …
Continue reading at hvg.ece.concordia.ca (PDF) (other versions)

Classifications

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