Rajski et al., 2024 - Google Patents
A nonlinear stream cipher for encryption of test patterns in streaming scan networksRajski et al., 2024
- Document ID
- 16018297887545197591
- Author
- Rajski J
- Trawka M
- Tyszer J
- Włodarczak B
- Publication year
- Publication venue
- IEEE Transactions on Circuits and Systems I: Regular Papers
External Links
Snippet
With the biennial doubling of the number of transistors in a given area of silicon, contemporary integrated circuits (IC) are forging more and more often and will continue to forge complex system-on-chip (SoC) designs. Their equally complex manufacturing and in …
- 238000012360 testing method 0 title abstract description 141
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/582—Pseudo-random number generators
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
- H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
- H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/588—Random number generators, i.e. based on natural stochastic processes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
- G01R31/318385—Random or pseudo-random test pattern
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
- G06F2207/7219—Countermeasures against side channel or fault attacks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/08—Randomization, e.g. dummy operations or using noise
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Sengar et al. | Secured flipped scan-chain model for crypto-architecture | |
| Yang et al. | Secure scan: A design-for-test architecture for crypto chips | |
| Cui et al. | Static and dynamic obfuscations of scan data against scan-based side-channel attacks | |
| Azar et al. | From cryptography to logic locking: A survey on the architecture evolution of secure scan chains | |
| Rahman et al. | Security assessment of dynamically obfuscated scan chain against oracle-guided attacks | |
| Liu et al. | Scan-based attacks on linear feedback shift register based stream ciphers | |
| CN106646203A (en) | Dynamic mixed scanning chain structure for protecting integrated circuit chip from being attacked through scanning chain | |
| Rahman et al. | CSST: an efficient secure split-test for preventing IC piracy | |
| Cerda et al. | An efficient FPGA random number generator using LFSRs and cellular automata | |
| Rajski et al. | A lightweight true random number generator for root of trust applications | |
| Karmakar et al. | Hardware IP protection using logic encryption and watermarking | |
| Banik et al. | Improved scan-chain based attacks and related countermeasures | |
| Thangam et al. | A novel logic locking technique for hardware security | |
| Huang et al. | Trace buffer attack on the AES cipher | |
| Thiemann et al. | On integrating lightweight encryption in reconfigurable scan networks | |
| Rajski et al. | A nonlinear stream cipher for encryption of test patterns in streaming scan networks | |
| Rudra et al. | Designing stealthy trojans with sequential logic: A stream cipher case study | |
| Subramanian et al. | Adaptive counter clock gated S-Box transformation based AES algorithm of low power consumption and dissipation in VLSI system design | |
| Talukdar et al. | TaintLock: Hardware IP Protection Against Oracle-Guided and Oracle-Reconstruction Attacks | |
| Krishnan et al. | Modelling of Random Number Generator based on PUFs and LFSR for secret key generation | |
| Rajski et al. | H 2 B: Crypto Hash Functions Based on Hybrid Ring Generators | |
| Likhithashree et al. | Area-efficient physically unclonable functions for FPGA using ring oscillator | |
| Rajski et al. | Test Data Encryption with a New Stream Cipher | |
| Lodha et al. | On-chip comparison based secure output response compactor for scan-based attack resistance | |
| Raut et al. | Stream cipher design using cellular automata implemented on FPGAs |