Anuraj et al., 2024 - Google Patents
Study and Experimental Analysis of FIR Hardware Architecture for Real-time Multimedia ApplicationsAnuraj et al., 2024
- Document ID
- 15685420551691415241
- Author
- Anuraj V
- Vaithiyanathan D
- Publication year
- Publication venue
- 2024 First International Conference on Innovations in Communications, Electrical and Computer Engineering (ICICEC)
External Links
Snippet
For effective Digital Signal Processing (DSP) processor design, optimizing area, power, and delay is essential to meet the needs of digital signal processing applications. This paper focuses on designing a high-speed Finite Impulse Response (FIR) filter incorporating …
- 238000004458 analytical method 0 title description 5
Classifications
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- G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
- G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
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