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Cantin et al., 2005 - Google Patents

Improving multiprocessor performance with coarse-grain coherence tracking

Cantin et al., 2005

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Document ID
13468404389415225609
Author
Cantin J
Lipasti M
Smith J
Publication year
Publication venue
32nd International Symposium on Computer Architecture (ISCA'05)

External Links

Snippet

To maintain coherence in conventional shared-memory multiprocessor systems, processors first check other processors' caches before obtaining data from memory. This coherence checking adds latency to memory requests and leads to large amounts of interconnect traffic …
Continue reading at web.stanford.edu (PDF) (other versions)

Classifications

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    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
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