Scott et al., 1986 - Google Patents
A fast VLSI multiplier for GF (2 m)Scott et al., 1986
- Document ID
- 12116810434553027543
- Author
- Scott P
- Tavares S
- Peppard L
- Publication year
- Publication venue
- IEEE Journal on selected Areas in Communications
External Links
Snippet
Multiplication in the finite field GF (2^{m}) has particular computational advantages in data encryption systems. This paper presents a new algorithm for performing fast multiplication in GF (2^{m}), which is O (m) in computation time and implementation area. The bit-slice …
- 238000013461 design 0 abstract description 6
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5332—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by skipping over strings of zeroes or ones, e.g. using the Booth Algorithm
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/724—Finite field arithmetic
- G06F7/726—Inversion; Reciprocal calculation; Division of elements of a finite field
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5443—Sum of products
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Scott et al. | A fast VLSI multiplier for GF (2 m) | |
| Kim et al. | A digit-serial multiplier for finite field GF (2/sup m/) | |
| Okada et al. | Implementation of elliptic curve cryptographic coprocessor over GF (2m) on an FPGA | |
| Wang et al. | A high-speed residue-to-binary converter for three-moduli (2/sup k/, 2/sup k/-1, 2/sup k-1/-1) RNS and a scheme for its VLSI implementation | |
| US20030135530A1 (en) | Flexible galois field multiplier | |
| JP2005512184A (en) | Galois field expansion, integration / integration addition, product-sum operation | |
| Bisheh Niasar et al. | Efficient hardware implementations for elliptic curve cryptography over Curve448 | |
| Scott et al. | Architectures for exponentiation in GF (2/sup m/) | |
| US7155473B2 (en) | High-speed parallel-prefix modulo 2n-1 adders | |
| Petra et al. | A novel architecture for galois fields GF (2^ m) multipliers based on mastrovito scheme | |
| Daneshbeh et al. | A class of unidirectional bit serial systolic architectures for multiplicative inversion and division over GF (2/sup m/) | |
| US8909510B2 (en) | LFSR emulation | |
| Joshi et al. | A new parallel algorithm for CRC generation | |
| Hasan et al. | Efficient architectures for computations over variable dimensional Galois fields | |
| WO2000065433A9 (en) | Method for multiplication in galois fields using programmable circuits | |
| Jeong et al. | VLSI array synthesis for polynomial GCD computation and application to finite field division | |
| Mekhallalati et al. | Novel radix finite field multiplier for GF (2m) | |
| Laxman et al. | FPGA implementation of different multiplier architectures | |
| Ferrer et al. | A fast finite field multiplier | |
| Benaissa et al. | CMOS VLSI design of a high-speed Fermat number transform based convolver/correlator using three-input adders | |
| Bharathwaj et al. | An alternate approach to modular multiplication for finite fields [GF (2/sup m/)] using Itoh Tsujii algorithm | |
| Madhuri et al. | Analysis of reconfigurable multipliers for integer and Galois field multiplication based on high speed adders | |
| Chiou et al. | Gaussian normal basis multiplier over GF (2m) using hybrid subquadratic‐and‐quadratic TMVP approach for elliptic curve cryptography | |
| Au et al. | A (4: 2) adder for unified GF (p) and GF (2 n) Galois field multipliers | |
| Wei | VLSI architectures of divider for finite field GF (2/sup m/) |