Liu et al., 2011 - Google Patents
A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequenceLiu et al., 2011
- Document ID
- 664341403601872145
- Author
- Liu P
- Hsiao J
- Chang H
- Lee C
- Publication year
- Publication venue
- 2011 Proceedings of the ESSCIRC (ESSCIRC)
External Links
Snippet
This paper presents a DPA-resistant AES crypto engine. The DPA countermeasure circuit is combined with a self-generated random number generator to eliminate an extra circuit for generating random bits. The cell area for the DPA-resistant AES crypto engine is 0.104 mm …
- 230000015556 catabolic process 0 abstract description 8
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/002—Countermeasures against attacks on cryptographic mechanisms
- H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/582—Pseudo-random number generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/588—Random number generators, i.e. based on natural stochastic processes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
- H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
- H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
- G06F2207/7219—Countermeasures against side channel or fault attacks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
- H04L9/0869—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving random numbers or seeds
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/08—Randomization, e.g. dummy operations or using noise
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/04—Masking or blinding
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Singh et al. | Improved power/EM side-channel attack resistance of 128-bit AES engines with random fast voltage dithering | |
| Tokunaga et al. | Securing encryption systems with a switched capacitor current equalizer | |
| Bellizia et al. | Secure double rate registers as an RTL countermeasure against power analysis attacks | |
| Kumar et al. | A time-/frequency-domain side-channel attack resistant AES-128 and RSA-4K crypto-processor in 14-nm CMOS | |
| Liu et al. | A true random-based differential power analysis countermeasure circuit for an AES engine | |
| Liu et al. | A low overhead DPA countermeasure circuit based on ring oscillators | |
| Shahverdi et al. | Lightweight side channel resistance: threshold implementations of S imon | |
| Moradi et al. | One attack to rule them all: Collision timing attack versus 42 AES ASIC cores | |
| US11194933B2 (en) | Circuits supporting improved side channel and fault injection attack resistance | |
| Kumar et al. | A 4900-$\mu $ m 2 839-Mb/s side-channel attack-resistant AES-128 in 14-nm CMOS with heterogeneous sboxes, linear masked MixColumns, and Dual-Rail key addition | |
| Liu et al. | A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence | |
| Bahrami et al. | Lightweight implementation of the lowmc block cipher protected against side-channel attacks | |
| Jain et al. | A novel tampering attack on AES cores with hardware trojans | |
| Zhang et al. | Power side channels in security ICs: hardware countermeasures | |
| Jayasinghe et al. | Quadseal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks | |
| Mayhew et al. | On-chip nanoscale capacitor decoupling architectures for hardware security | |
| Kumar et al. | An 8.3-to-18Gbps reconfigurable SCA-resistant/dual-core/blind-bulk AES engine in Intel 4 CMOS | |
| Moos | Unrolled cryptography on silicon: a physical security analysis | |
| Kumar et al. | A 7-Gbps SCA-resistant multiplicative-masked AES engine in Intel 4 CMOS | |
| Zhu et al. | Counteracting leakage power analysis attack using random ring oscillators | |
| Saeki et al. | A design methodology for a DPA-resistant cryptographic LSI with RSL techniques | |
| Zhang et al. | FinFET-based power management for improved DPA resistance with low overhead | |
| Jayasinghe et al. | FPGA based countermeasures against side channel attacks on block ciphers | |
| Abdulgadir et al. | Side-channel resistant implementations of a novel lightweight authenticated cipher with application to hardware security | |
| Ghosal et al. | Differential fault analysis attack-tolerant hardware implementation of AES. |