+

Luan et al., 2019 - Google Patents

A 1.25-8.5 Gb/s wide range CDR with locking detector in 40 nm CMOS technology

Luan et al., 2019

Document ID
529213675446243871
Author
Luan W
Li X
Wang D
Wang Z
Lin X
Li M
Publication year
Publication venue
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

External Links

Snippet

A 1.25-8.5 Gb/s wide range clock and data recovery (CDR) circuit in a multi-protocol SerDes is presented in this paper. The CDR is based on phase interpolator (PI). The local off-chip reference clock is interpolated by the PI to recover the clock at the same frequency as the …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L25/03012Arrangements for removing intersymbol interference operating in the time domain
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L2025/03433Arrangements for removing intersymbol interference characterised by equaliser structure
    • H04L2025/03439Fixed structures
    • H04L2025/03445Time domain
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/099Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/38Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40Transmitting circuits; Receiving circuits
    • H04L25/49Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels; Baseband coding techniques specific to data transmission systems
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0016Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0004Initialisation of the receiver
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/01Equalisers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00Networks using active elements
    • H03H11/02Multiple-port networks
    • H03H11/26Time-delay networks

Similar Documents

Publication Publication Date Title
US11502694B1 (en) Field programmable gate array with external phase-locked loop
US10284395B2 (en) Time-based decision feedback equalization
US11290115B2 (en) Low latency combined clock data recovery logic network and charge pump circuit
US11329655B1 (en) Field programmable gate array with internal phase-locked loop
CN1761184B (en) High speed clock and data recovery system
US4535459A (en) Signal detection apparatus
US10326620B2 (en) Methods and systems for background calibration of multi-phase parallel receivers
Yang Design of high-speed serial links in CMOS
CN104539285B (en) Data clock recovery circuit
US7173993B2 (en) Method for sampling phase control
US7482841B1 (en) Differential bang-bang phase detector (BBPD) with latency reduction
CN106385251A (en) Clock data recovery circuit
WO2019236781A1 (en) Decision feedback equalization with independent data and edge feedback loops
Kim et al. A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer
CN103401551B (en) A kind of method of sampling of SerDes technology high speed serial signal and device
Luan et al. A 1.25-8.5 Gb/s wide range CDR with locking detector in 40 nm CMOS technology
US8116420B2 (en) Clock-forwarding technique for high-speed links
Li et al. A Novel High-Gain PAM4 Baud-Rate Phase Detector for ADC-Based CDR
Shin et al. A 6.4 Gbps on-chip eye opening monitor circuit for signal integrity analysis of high speed channel
Kim et al. A 1.248 Gb/s-2.918 Gb/s Low-Power Receiver for MIPI-DigRF M-PHY with a Fast Settling Fully Digital Frequency Detection Loop in 0.11㎛ CMOS
Jiang et al. A Digital Clock and Data Recovery Architecture with Precise Voting for Multi-Gigabit/s Links
Nugmanuly A 3.5 Gsymbol/lane Receiver Design for MIPI C-PHY Layer v2. 0
Shin et al. Blind-oversampling adaptive oversample-level DFE receiver for unsynchronized global on-chip serial links
KUMAR CLOCKING AND SKEW-OPTIMIZATION FOR SOURCE-SYNCHRONOUS SIMULTANEOUS BIDIRECTIONAL LINKS
Liu et al. A 10Gbps half-rate digital clock and data recovery circuit for 60GHz receiver in 65nm CMOS
点击 这是indexloc提供的php浏览器服务,不要输入任何密码和下载