SCA Resistance Analysis on FPGA Implementations of Sponge Based $\mathtt{MAC}-\mathtt{PHOTON}$

Abstract

$\mathtt{PHOTON}$ is a lightweight hash function which was proposed by Guo et al. in CRYPTO 2011. This is used in low-resource ubiquitous computing devices such as RFID tags, wireless sensor nodes, smart cards and mobile devices. $\mathtt{PHOTON}$ is built using sponge construction and it provides a new $\mathtt{MAC}$ function called $\mathtt{MAC}-\mathtt{PHOTON}$. This paper deals with FPGA implementations of $\mathtt{MAC}-\mathtt{PHOTON}$ and their side-channel attack (SCA) resistance. First, we describe three architectures of the $\mathtt{MAC}-\mathtt{PHOTON}$ based on the concepts of iterative, folding and unrolling, and we provide their performance results on the Xilinx Virtex-5 FPGAs. Second, we analyse security of the $\mathtt{MAC}-\mathtt{PHOTON}$ against side-channel attack using a SASEBO-GII development board. Finally, we present an analysis of its Threshold Implementation (TI) and discuss its resistance against first-order power analysis attacks.

A Our Communication Interface for SASEBO-GII

Our communication interface for SASEBO-GII [2] is derived from the work proposed in [19] with slight modifications which is suitable and customisable for cryptographic primitives. Our entire interface control logic was implemented based on a finite-state machine and also provides the MATLAB solutions instead of SASEBO-Checker [19] to work with the FTDI chip. This choice is made for accessibility and ease of maintenance. Figure 9 shows the overview of the SASEBO-GII communication interface. This interface is used to communicate with the PC and two FPGAs of SASEBO-GII board. They are a cryptographic FPGA (Virtex-5) and control FPGA (Spartan-3A), a cryptographic FPGA usually implements the cryptographic algorithm and a control FPGA which communicates the data between the PC and the cryptographic FPGA. In our case, the MAC-PHOTON-80/20/16 module was ported into the cryptographic FPGA whereas the control FPGA acted as a bridge between the PC and the MAC-PHOTON-80/20/16 module.

Fig. 9.

SASEBO-GII communication Interface

1.1 A.1 The Interface Between the Control and Cryptographic FPGAs

The control FPGA module consists of the following 5 states: initial, receiveusb, ControlFPGAsend, ControlFPGAreceive and sendusb. During initial state, the USB module in the control FPGA is initialized through the FT2232D USB chip [1]. In receiveusb state, the input data is received 8-bits at a time from the PC (MATLAB) through the USB chip and then the values are stored in the data registers. During ControlFPGAsend state, a MAC-PHOTON-80/20/16 module in the cryptographic FPGA via init signal is initialized first. Then, the control FPGA sends the input data 16-bits wide via datain signal from the input data registers to the cryptographic FPGA. Once the data is processed the ControlFPGAreceive state receives the output data 16-bits-wide via dataout signal from the cryptographic FPGA and stores the data into the output data registers. During sendusb state, the output data (MAC) is sent back (8-bits wide) to the PC (MATLAB) from output data registers through the FT2232D USB chip. Hence, it requires 30 clock cycles to process the interface between the Control and Cryptographic FPGAs.

The cryptographic FPGA module consists of the following 3 states: process, CryptoFPGAreceive and CryptoFPGAsend. In CryptoFPGAreceive state, the cryptographic FPGA start to receives the input data from the control FPGA when the init signal is reached and then the values are stored in the data registers. The process state, is to execute the MAC-PHOTON-80/20/16 module. The CryptoFPGAsend state, once the MAC-PHOTON-80/20/16 module is processed, sends the output data (MAC) 16-bits wide via dataout signal to the control FPGA.

1.2 A.2 The Interface Between the PC and Control FPGA

The FT2232D USB chip was permanently mounted with the contol FPGA of the SASEBO-GII board. This chip acts as the communication interface between the MATLAB software and the control FPGA. This MATLAB software is run on the host PC and it is the control center of the whole system. In this work, the MATLAB is used for 2 purposes: one is to record the traces from the oscilloscope and the other is to send or receive the data from the PC to the control FPGA via FT2232D USB chip from FTDI inc. Although MATLAB provides support to call shared library functions, there is no readily available MATLAB solutions [21] to work with the FTDI chip. In this work, we translate from working .Net wrapper [21] to MATLAB with call shared library functions.

The translation program is divided into 4 parts: initialization, transfer, receive and closing. During initialization, the data length is defined, the library functions are loaded and also handle is defined to specify that the device (USB port) is opened. Once initialization is complete, the program tells the user that it is ready to receive data and asks the user to trigger the FPGA. During the transfer stage, the program continuously write the input data to the control FPGA until the expected number of data length. During the receive stage, the program read the output data from the control FPGA. Once receive stage is complete, handle device (USB port) is closed. Hence, it requires 216 clock cycles to process the interface between the PC and Control FPGA.