Abstract
We present FPGA-implementation techniques to efficiently validate application readiness of a product for analog/mixed-signal (AMS) applications that lead to a reduction of overall runtime by two orders of magnitude on the example of a power conversion application compared to state-of-the-art simulation based approaches. Further, we use this example to analyze area utilization, timing impact and scalability at increased application complexity. The open source synthesizable model generator for mixed-signal blocks msdsl is extended to support reconfigurable variables within a model description. Further, the control API of the open source FPGA prototyping automation anasymod is enhanced to allow updating these variable values on FPGA at runtime. The end-result is a unique framework for application scenario driven product validation that to our knowledge for the first time allows reconfiguration of analog dynamics on FPGA at runtime and leverages benchmark AMS system simulation throughput on FPGA to enables fast system property sweeping at different modeling abstractions.
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The authors would like to thank the Federal Ministry of Education and Research (Germany) via the KI4BoardNet program for supporting this work.
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Rutsch, G., Maier, K., Ecker, W. (2024). FPGA-Implementation Techniques to Efficiently Test Application Readiness of Mixed-Signal Products. In: Elfadel, I.(.M., Albasha, L. (eds) VLSI-SoC 2023: Innovations for Trustworthy Artificial Intelligence. VLSI-SoC 2023. IFIP Advances in Information and Communication Technology, vol 680. Springer, Cham. https://doi.org/10.1007/978-3-031-70947-0_10
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