🙈 Volkswagen detects when your tests are being run in a CI server, and makes them pass.

HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

📕 A book about Algorithms and Data Structures (PL)

🛠 Python project template generator with batteries included

Final project for Machine Learning

OpenTitan: Open source silicon root of trust

An experimental, FPGA-driven tester for SO-DIMM DDR5 memory sticks

This project will compile verilog (a hardware description language) into factorio blueprints.

Chisel examples and code snippets

Chisel: A Modern Hardware Design Language

Generator Bootcamp Material: Learn Chisel the Right Way

A template project for beginning new Chisel work

AXI interface modules for Cocotb

Build your hardware, easily!

LiteX boards files

Bootprint template to convert JSON-schema into readble HTML, this repository has moved to https://github.com/bootprint/bootprint-monorepo/tree/master/packages/bootprint-json-schema

Convert Complex JSON Schemas into Markdown Documentation

A C++ cooperative threading library

Linux on LiteX-VexRiscv

My personal page

Sejm infographic app

AXI Formal Verification IP

Modular visual interface for GDB in Python

RISC-V out-of-order core for education and research purposes