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caliptra-ss Public
Forked from chipsalliance/caliptra-ssHW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
SystemVerilog Apache License 2.0 UpdatedOct 1, 2025 -
opentitan Public
Forked from lowRISC/opentitanOpenTitan: Open source silicon root of trust
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caliptra-rtl Public
Forked from chipsalliance/caliptra-rtlHW Design Collateral for Caliptra RoT IP
SystemVerilog Apache License 2.0 UpdatedMar 7, 2025 -
ibex Public
Forked from lowRISC/ibexIbex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
SystemVerilog Apache License 2.0 UpdatedMay 2, 2024 -
ot-sca Public
Forked from lowRISC/ot-scaSide-channel analysis setup for OpenTitan
Jupyter Notebook Apache License 2.0 UpdatedFeb 23, 2024 -
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riscv-isa-sim Public
Forked from riscv-software-src/riscv-isa-simSpike, a RISC-V ISA Simulator
C Other UpdatedApr 4, 2023 -
fusesoc Public
Forked from olofk/fusesocPackage manager and build abstraction tool for FPGA/ASIC development
Python BSD 2-Clause "Simplified" License UpdatedJul 26, 2022 -
coco-ibex Public
Forked from isec-tugraz/coco-ibexSystemVerilog Apache License 2.0 UpdatedJul 8, 2022 -
riscv-dv Public
Forked from chipsalliance/riscv-dvRandom instruction generator for RISC-V processor verification
Python Apache License 2.0 UpdatedMay 24, 2022 -
chipwhisperer-minimal Public
Forked from newaetech/chipwhisperer-minimalMinimal chipwhisperer that only supports the CW310
Python UpdatedMay 24, 2022 -
chipwhisperer Public
Forked from newaetech/chipwhispererChipWhisperer - the complete open-source toolchain for side-channel power analysis and glitching attacks
VHDL Other UpdatedMay 10, 2022 -
edalize Public
Forked from lowRISC/edalizeAn abstraction library for interfacing EDA tools
Python BSD 2-Clause "Simplified" License UpdatedApr 7, 2022 -
style-guides Public
Forked from lowRISC/style-guideslowRISC Style Guides
Creative Commons Attribution 4.0 International UpdatedJan 21, 2022 -
riscv-binutils-gdb Public
Forked from riscvarchive/riscv-binutils-gdbRISC-V backports for binutils-gdb. Development is done upstream at the FSF.
C GNU General Public License v2.0 UpdatedNov 30, 2021 -
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cv32e40x Public
Forked from openhwgroup/cv32e40x4 stage, in-order, compute RISC-V core based on the CV32E40P
SystemVerilog Other UpdatedAug 26, 2021 -
rebecca Public
Forked from isec-tugraz/rebeccaREBECCA is a tool for the formal verification of masked cryptographic hardware implementations that, given the netlist of a masked hardware circuit, determines if a correct separation between share…
Verilog Apache License 2.0 UpdatedFeb 25, 2021 -
riscv-compliance Public
Forked from lowRISC/riscv-complianceTEMPORARY FORK of the riscv-compliance repository
C BSD 3-Clause "New" or "Revised" License UpdatedOct 4, 2020 -
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lowrisc.github.io Public
Forked from lowRISC/lowrisc.github.ioGenerated html for the lowRISC site. PRs should go to the source repo https://github.com/lowrisc/lowrisc-site
HTML UpdatedMay 5, 2020 -
lowrisc-web Public
Forked from lowRISC/lowrisc-weblowrisc.org web site sources
HTML Apache License 2.0 UpdatedMay 5, 2020 -
vendor_example Public
A simple example showing how to use the OT vendor tool for using the usbdev in another project.
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