Verilog Implementation of an ARM LEGv8 CPU

FPGA Sound Blaster over LPC bus experiments

Design of a Processor Microarchitecture Supporting a Chosen Subset of RISC-V ISA Instructions.

Reduced MIPS 32-bit Processor

A 16-bit, 5-stage RISC processor. RTL description in Verilog. Includes assembler, simulator, and example programs.

A custom processor implemented in Verilog HDL for image down sampling for UOM's EN3030 Circuits and Systems Design module ❄

Computer Architecture-MIPS Processor simulation in verilog with self developed ISA

8-bit CPU with custom ISA + assembler

A custom RISC 16-bit CPU running at 50MHz on an FPGA