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Repo of high bandwidth memory papers, codes, ...
This repository contains various patches to the OSCI systemc distribution to make it possible to compile the sources with latest GCC versions. While I am publishing the patches under LGPL license, …
A hardware accelerator for General Matrix Multiply, developed in SystemC using ESP.
An EDA toolchain for integrated core-memory interval thermal simulations of 2D, 2.5, and 3D multi-/many-core processors
Verilog AXI components for FPGA implementation
A New Approach for Efficient Sequential Decoding of Static Huffman Codes
HotSpot v7.0 is an accurate and fast thermal model suitable for use in architectural studies.
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Synchronous FIFO design & verification using systemVerilog Assertions
A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.
DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
The memory model was leveraged from micron.
HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
A DDR3 memory controller in Verilog for various FPGAs
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
Source code of PyGAD, a Python 3 library for building the genetic algorithm and training machine learning algorithms (Keras & PyTorch).
Source code of the processing-in-memory simulator used in the GRIM-Filter paper published at BMC Genomics in 2018: "GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping using Processing-in…
An integrated power, area, and timing modeling framework for multicore and manycore architectures