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1. yuu_register_productor yuu_register_productor Public

   UVM register utility generation by inputting xls table

   JavaScript 39 23

2. yuu_apb yuu_apb Public

   UVM APB VIP, part of AMBA3&AMBA4 feature supported

   SystemVerilog 32 11

3. yuu_ahb yuu_ahb Public

   UVM AHB VIP

   SystemVerilog 87 21

4. yuu_vip_gen yuu_vip_gen Public

   UVM VIP architecture generator

   SystemVerilog 20 6

5. sv_shortreal_to_fp16 sv_shortreal_to_fp16 Public

   Transform SystemVerilog shortreal(float) type to FP16 bit vector according to IEEE 754, for AI chip verification etc.

   SystemVerilog

6. sv_docs sv_docs Public

   A UVM-style SystemVerilog HTML document generator, updated from the accellera git repo.

   Perl