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Showing results
JavaScript 6 1 Updated Jun 8, 2025

Comprehensive optical design, optimization, and analysis in Python, including GPU-accelerated and differentiable ray tracing via PyTorch.

Python 448 89 Updated Oct 7, 2025

GNSS-SDR, an open-source software-defined GNSS receiver

C++ 1,906 660 Updated Oct 11, 2025

Low cost motion capture system for room scale tracking

TypeScript 2,111 359 Updated May 25, 2024

Spectroscopy lock application using RedPitaya

Python 97 22 Updated Oct 6, 2025

CH55x USB to JTAG bridge

C 138 36 Updated Mar 12, 2025

RV-Debugger-BL702 Project, an opensource debugger implement

C 205 74 Updated Oct 31, 2024
Jupyter Notebook 106 15 Updated Oct 7, 2025

RSD: RISC-V Out-of-Order Superscalar Processor

SystemVerilog 1,102 109 Updated Oct 10, 2025

Guacamole with docker-compose using PostgreSQL, nginx with SSL (self-signed)

Shell 1,291 475 Updated Aug 18, 2025

Docker image for FreeRDP client with noVNC.

Makefile 2 4 Updated Oct 1, 2025

Authenticate Apache Guacamole users with PAM

Java 10 5 Updated Apr 15, 2020

An JLC PCB Fabrication Plugin for KiCad

Python 501 72 Updated Oct 3, 2025

Bus bridges and other odds and ends

Verilog 589 113 Updated Apr 14, 2025

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https:/…

Verilog 74 7 Updated Oct 7, 2025

CologneChip GateMate FPGA Module: GMM-7550

24 2 Updated Oct 8, 2025

A compact USB HID host FPGA core supporting keyboards, mice and gamepads.

Verilog 139 26 Updated Mar 22, 2025

A full analog GPS receiver using discrete rf components and TinyFPGA

C 150 11 Updated Aug 15, 2024

Sub-nanosecond time interval counter

C 40 12 Updated Oct 10, 2025

Generate bitstream from FPGA assembly.

C++ 24 4 Updated Sep 28, 2025

A test case for stress testing Tang Nano 4K and 9K and Primer 20K (Gowin FPGAs)

Verilog 45 3 Updated Dec 6, 2024

The simplest and most complete UI for your private docker registry v2 and v3

Riot 3,123 350 Updated Jul 20, 2025

Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numerical sauce. The best of all is that the sauce is not secret, b…

VHDL 12 2 Updated Sep 21, 2025

Small (Q)SPI flash memory programmer in Verilog

Verilog 64 13 Updated Nov 5, 2022

Affordable 2 GHz 3.2 GS/s 12 bit open-source open-hardware expandable USB oscilloscope

Verilog 309 66 Updated Oct 11, 2025

Convert Xilinx FPGA bitstream from the .bit format (as generated by Vivado) into the .bin format (as expected by Linux fpga_manager)

C 11 7 Updated Sep 5, 2023

VHDL PCIe Transceiver

VHDL 30 11 Updated Jul 2, 2020

Original FPGA platform

Verilog 69 17 Updated Oct 9, 2025
Verilog 70 14 Updated Aug 19, 2024
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