OpenXuantie - OpenC910 Core

2D Systolic Array Multiplier

A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.

verilog实现TPU中的脉动阵列计算卷积的module

2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

IC implementation of Systolic Array for TPU

USB 2.0 Device IP Core

一步一步写MIPS CPU

🎓电子科技大学 📔课程资料

包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等

A very simple and easy to understand RISC-V core.

This project uses a variety of advanced voiceprint recognition models such as EcapaTdnn, ResNetSE, ERes2Net, CAM++, etc. It is not excluded that more models will be supported in the future. At the …

端到端语音唤醒工具箱，从模型训练到模型推理。

You can find the speech algorithms you want here

本项目对中文版《动手学深度学习》中的代码进行了PyTorch实现并整理为PDF版本供下载

✔️李沐 【动手学深度学习】课程学习笔记：使用pycharm编程，基于pytorch框架实现。