Qrisc cpu based on my qrisc32, in different languages
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SystemVerilog - done, original and quite old one added usage of Verilator for running test.
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Bluespec System Verilog - redesigned version of Systemverilog, and has got different instruction codes. EX stage runs clock 2 cycles to allow mult and adders to finish. Added AXI for instruction reading and read/write data
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Bluespec Classic - TBD
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Amaranth - TBD
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Clash - TBD