Temporary solution to not surprise anyone running the test programs with humongous log files.

* wip: basic csr

* wip

* wip

* refactor: Rename process queue -> change queue

* refactor: Rename event_q -> event_queue

* refactor: Move queue processing to separate method

* refactor: Move cycle log to separate method

* refactor: Move tick logic into separate method

* refactor: Rename step() to cycle()

* fix: Drain queues after step cycle

* refactor: Make sim.tick private

* refactor: Make sim.step reuse sim.cycle

* feat: Add reset method to simulator

* chore: Remove comment

* docs: Update comment

* refactor: sim step logic

* refactor: move sim step tests into own class

* refactor: sim step logic 2

* fix(csr): Add separate read and write address ports

* refactor: Use fixture for IDStage tests

* fix: Remove sens list from CSR read addr

* feat: Add CSRRW instruction

* perf: Make csr read interface function based

* refactor(sim): Add log method

* fix: Drain queues after sim

* fix(csr): Don't warn when CSR 0 accessed

* chore(decode): Remove unused csr ports

* fix(csr): Make sure we is set for regfile

* feat: Add CSR unit to SingleCycle model

* feat: Add SingleCycle core test

* chore(port): Remove usused variable

* Add CSRRS instruction

* Add CSRRC instruction

* fix(csr): Handle special cases

* Add integer reg defs

* Add csrrw no read test

* Fix csrrw no read logic + add csrrwi

* Fix csrrwi in EXStage

* csrrwi: Add rd=x0 logic

* Add csrrsi

* Add csrrci

* Add is_csr signal

* Add csrrs rs1=x0 test

* refactor: Remove is_csr signal

We can simply extend the wb_sel signal.

* docs: Update CHANGELOG

* style: PEP8

* fix: Fixture order

* fix: Make sim fixture autouse

* fix: Remove log messages

* refactor: Use logger warning instead of warn

* feat: Enable logs for tests

Logs are now disabled by default, but will be enabled for tests.

* style: PEP8