Transforms complex documents like PDFs into LLM-ready markdown/JSON for your Agentic workflows.

A DSL for formal verification of hardware and software systems using Rocq/Coq.

Showcase examples for EPFL logic synthesis libraries

UltraRAG 2.0: Less Code, Lower Barrier, Faster Deployment! MCP-based low-code RAG framework, enabling researchers to build complex pipelines to creative innovation.

An advanced automated reasoning tool for memory consistency model specifications.

Pick your favorite language to verify your chip.

Natural language tactics to teach mathematics using Lean 4

IOMMU IP compliant with the RISC-V IOMMU Specification v1.0

Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".

A library of Coq definitions, theorems, and tactics. [maintainers=@gmalecha,@liyishuai]

Text-audio foundation model from Boson AI

Binary Neural Network in Pytorch

A Verilog Synthesis Regression Test

Experiments on automation for Lean

RTLMeter benchmark suite

Hack4Her: Logic Synthesis for AI

ICSE 2025: Fuzzing MLIR compilers with Custom Mutation Synthesis

E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)

slime is a LLM post-training framework aiming at scaling RL.

a simple C-to-Verilog compiler

Nano vLLM

An experimental repository developing formal tools to specify financial smart contracts in ConCert (Coq). Corresponds to the text of my PhD thesis.

Open stadard cell library for open 28nm process