This repository contains code example projects for the AURIX™ Development Studio.

平头哥无剑100开源SoC平台（双核E902，安全启动，BootROM，IOPMP，Mailbox，RSA-2048，SHA-2， WS2812，Flash）

STM32-style peripheral modules (GPIO, TIM, UART, etc.) and general graphic modules (drivers, algorithms ...) written in Verilog/Chisel/SpinalHDL with APB/AHB/AXI interfaces. Includes a RISC-V SoC e…

An open-source static random access memory (SRAM) compiler.

AXI总线连接器

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

平头哥玄铁C910的LLVM工具链支持，由PLCT实验室提供，非官方版本

TradingAgents: Multi-Agents LLM Financial Trading Framework

Yosys Open SYnthesis Suite

使用小爱音箱播放音乐，音乐使用 yt-dlp 下载。

RISC-V CPU Core

一种通用CNN加速器

a fast, scalable, multi-language and extensible build system

A GPS bicycle speedometer that supports offline maps and track recording

wallabag is a self hostable application for saving web pages: Save and classify articles. Read them later. Freely.

BaseJump STL: A Standard Template Library for SystemVerilog

The OpenPiton Platform

OpenSoC Fabric - A Network-On-Chip Generator

Verilator open-source SystemVerilog simulator and lint system

mflowgen -- A Modular ASIC/FPGA Flow Generator

AXI crossbar dv project for UVM learners.

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

FuseSoC standard core library

An AI Hedge Fund Team

A collective list of free APIs

Package manager and build abstraction tool for FPGA/ASIC development

FinRL®: Financial Reinforcement Learning. 🔥