+
Skip to content
View hucan7's full-sized avatar

Block or report hucan7

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

The Ultra-Low Power RISC-V Core

Verilog 1,621 391 Updated Aug 6, 2025

Scala based HDL

Scala 1,856 363 Updated Oct 9, 2025

FuseSoC-based SoC for VeeR EH1 and EL2

Verilog 326 73 Updated Dec 11, 2024

Package manager and build abstraction tool for FPGA/ASIC development

Python 1,344 263 Updated Oct 10, 2025

OpenXuantie - OpenE906 Core

Verilog 141 74 Updated Jun 28, 2024

OpenXuantie - OpenC910 Core

Verilog 1,328 355 Updated Jun 28, 2024

OpenXuantie - OpenC906 Core

Verilog 370 114 Updated Jun 28, 2024

cocotb: Python-based chip (RTL) verification

Python 2,107 584 Updated Oct 10, 2025

OpenSource HummingBird RISC-V Software Development Kit

C 164 52 Updated Dec 5, 2023

Build your hardware, easily!

C 3,549 651 Updated Oct 8, 2025
点击 这是indexloc提供的php浏览器服务,不要输入任何密码和下载