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Commits on Sep 28, 2023

• [MemCpyOptimizer] Support scalable vectors in performStackMoveO… (#67632)

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• [RISCV] Improve constant materialization by using a sequence that end… (#66943)

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Commits on Sep 27, 2023

• [RISCV][GISel] Remove source constraint from selectCopy and use it fo… (#67207)

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• [RISCV] Fix -Wsign-compare warning. NFC

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• [TableGen][GISel] Add PtrValueTypeByHwMode to be able to vary … (#67501)

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• [RISCV] Fix a crash from trying to truncate an FP type in lowerBuildV… (#67488)

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Commits on Sep 26, 2023

• [LLParser] Merge xor constantexpr parsing with add/mul/shl/lshr/ashr. (#67371)

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• [RISCV] Correct Zhinx load/store patterns to use AddrRegImm.

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• [RISCV] Autogenerate tests to add missing CHECK lines. NFC

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• [RISCV] Disable constant hoisting for mul by one more/less than a pow… (#67385)

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• [RISCV] Explicitly create IMPLICIT_DEF instead of UNDEF for vectors i… (#67369)

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Commits on Sep 25, 2023

• [RISCV] Don't set KILL flag on X0 in RISCVInstrInfo::movImm.

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• [LLParser] Remove unnecessary switch from the handling of the remaini… (#67362)

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Commits on Sep 23, 2023

• [RISCV][GISel] Emit G_CONSTANT 0 as a copy from X0. (#67202)

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• [RISCV][GISel] Add test showing missed opportunity to use X0 for the LHS of sub for negate.

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Commits on Sep 22, 2023

• [RISCV][GISel] Implement instruction selection for G_PHI and G_BRCOND.

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• [RISCV][GISel] Add a post legalizer combiner and enable a couple comb… (#67053)

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• [RISCV] Truncate constants to eltwidth before checking simm5 when con… (#67062)

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Commits on Sep 21, 2023

• Recommmit "[RISCV] Improve contant materialization to end with 'not' if the cons… (#66950)"

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• Revert "[RISCV] Improve contant materialization to end with 'not' if the cons… (#66950)"

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Commits on Sep 20, 2023

• [RISCV] Improve contant materialization to end with 'not' if the cons… (#66950)

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Commits on Sep 19, 2023

• [RISCV] Add more instructions for the short forward branch optimization. (#66789)

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• [RISCV] Fix bad isel predicate handling for Ztso. (#66739)

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Commits on Sep 18, 2023

• [RISCV][GISel] Add initial pre-legalizer combiners copying from AArch64.

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• [SelectionDAG][RISCV] Mask constants to narrow size in TargetLowering::expandUnalignedStore.

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• [RISCV] Add test case to show bad codegen for unaligned i64 store of a large constant.

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• [SelectionDAG][RISCV][PowerPC][X86] Use TargetConstant for immediates for ISD::PREFETCH. (#66601)

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Commits on Sep 17, 2023

• [RISCV] Use getConstantOperandVal. NFC

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• [RISCV] Reuse existing XLenVT variable. NFC

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Commits on Sep 15, 2023

• [RISCV][GlobalISel] Select ALU GPR instructions

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Commits on Sep 6, 2023

• [RISCV] Disable machine verifier in gisel-commandline-option.ll. NFC

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• [RISCV] Use add.uw for (or (and X, 0xFFFFFFFF), Y) if Y has zeroes in the lower 32 bits. (#65402)

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Commits on Sep 5, 2023

• [RISCV][GISel] Add gisel-commandline-option.ll similar to AArch64. (#65299)

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Commits on Sep 4, 2023

• [RISCV] Add more files to .github/CODEOWNERS (#65234)

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• [X86] Add more files to .github/CODEOWNERS (#65235)

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