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ojack / hydra
Forked from hydra-synth/hydraLivecoding networked visuals in the browser
TinyQV Byte Peripheral Template
Personal project that automates resume adaptation using LLMs. Converts .docx resumes to Markdown, tailors them to job descriptions with GPT-4o-mini or Gemini, and exports clean HTML and PDF resumes…
A simple 16bit system-on-chip (SoC) consisting of a CPU and GPU
A Fourier Analysis analysis tool to compare audio produced by gaming hardware
SDK for Greenwaves Technologies' GAP8 IoT Application Processor
Central hub for RealtimeSanitizer and its associated tooling
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Learning to do things with the Skywater 130nm process
Project to use a Raspberry Pi as a NES graphics accelerator
A Basic programmable educational retro-minicomputer equipped with a MOS 6502
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
RT-Thread is an open source IoT Real-Time Operating System (RTOS). https://rt-thread.github.io/rt-thread/
CPU Adventure 2 challenge from the Dragon CTF 2019
CPU Adventure task from Dragon CTF 2019 teaser
RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card
Commodore C64 core for the Tang Nano 20K Primer 25K Mega 60k Mega 138K Pro Console60k FPGA
FPGA implementation of DEC PDP-1 computer (1959) in Verilog, with CRT, Teletype and Console.
A minimal GPU design in Verilog to learn how GPUs work from the ground up
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
RISC-V implementation of rv32i for FPGA board Tang Nano 9K utilizing on-board burst PSRAM and flash