X-HEEP Soc + STRELA CGRA

STReaming ELAstic CGRA accelerator for X-HEEP

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Official OpenOCD Read-Only Mirror (no pull requests)

OpenBLAS is an optimized BLAS library based on GotoBLAS2 1.13 BSD version.

FuseSoC standard core library

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.

IMPRESS - IMplementation of Partial REconfigurable SystemS

Elastic Coarse-Grained Reconfigurable Architecture Generator

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

An abstraction library for interfacing EDA tools

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Package manager and build abstraction tool for FPGA/ASIC development

eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V

Common SystemVerilog components

🌸 A command-line fuzzy finder

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more