Microsoft BASIC for 6502 Microprocessor - Version 1.1

Small portable AES128/192/256 in C

Source code of the paper "Lord of the Ring(s): Side Channel Attacks on the CPU On-Chip Ring Interconnect Are Practical"

Development for the official WCA scramble server

Scripts for creating the CHERIoT dev container

OpenMZ, a security kernel for RISC-V targeting secure coprocessors and secure embedded systems.

Ariane SDK containing RISC-V tools and Buildroot

Fork of OpenOCD that has RISC-V support

RISC-V Open Source Supervisor Binary Interface

The OpenPiton Platform

SCAAML: Side Channel Attacks Assisted with Machine Learning

Debugging details for various projects

C64's VIC-II video chip on a Tang Nano 9k FPGA with HDMI

HSYNC and VSYNC examples.

The wolfSSL library is a small, fast, portable implementation of TLS/SSL for embedded devices to the cloud. wolfSSL supports up to TLS 1.3 and DTLS 1.3!

A pure Python implementation of AES, with optional CBC, PCBC, CFB, OFB and CTR cipher modes.

RISC-V Scratchpad

This repository contains Solutions & Setup for competitive programming competitions and Templates for Data Structures and Algorithms, written in C++.

A base container image populated with the dependencies to build the RISC-V Documentation.

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

RISC-V Opcodes

The Adventures of OS

Cross compiling toolchains in Docker images

Xv6 for RISC-V

RISC-V Assembly Programmer's Manual

Construct: Declarative data structures for python that allow symmetric parsing and building

A scalable set of icons handcrafted with ❤️ by GitHub

DIY your own kernal and operating system for the C64