80186 compatible SystemVerilog CPU core and FPGA reference design

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

Time And Relative Dimension In Logic (TARDIL)

Rendez-vous synchronisation mechanism for C++

SERV - The SErial RISC-V CPU

Documentation on how to perform static timing, with detailed examples on writing constraints and how to validate timing reports.

Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC

AT command interface for any modem

The VESC motor control firmware

Firmware for stm32f051 based speed controllers for use with mutirotors

serial interface library for renesas microcontrollers in boot mode

Oxford Oberon-2 compiler

OBS複数サイト同時配信プラグイン

AviSynth with improvements

A decorator to profile the run time of functions/classes/modules

A compact way to encode Unicode strings

Pure-C utility for programming AVR devices with UPDI interface using a standard TTL serial port