A web-based VHDL/SystemVerilog AXI4 register bank generator for FPGA and ASIC projects. Sign-up for free at airhdl.com.
airhdl
Web-based VHDL/SystemVerilog AXI4 register generator for FPGA and ASIC projects.
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- spi-to-axi-bridge Public
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
airhdl/spi-to-axi-bridge’s past year of commit activity - .github Public
airhdl/.github’s past year of commit activity - osvvm-demo Public
A project demonstrating how to use the OSVVM library and its Axi4LiteManager verification component to simulate an airhdl register bank.
airhdl/osvvm-demo’s past year of commit activity
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